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REJ09B0024-0600
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
8
H8/3802, H8/38004, H8/38002S, H8/38104 Group
Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series
H8/3802 Group H8/3802 H8/3801 H8/3800 H8/38004 H8/38003 H8/38002 H8/38001 H8/38000 H8/38002S Group H8/38002S H8/38001S H8/38000S H8/38104 H8/38103 H8/38102 H8/38101 H8/38100
H8/38004 Group
H8/38104 Group
Rev. 6.00 Revision Date: Mar 15, 2005
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 6.00 Mar 15, 2005 page ii of l
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 6.00 Mar 15, 2005 page iii of l
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 6.00 Mar 15, 2005 page iv of l
Preface
The H8/3802 Group, H8/38004 Group, and H8/38104 Group are single-chip microcomputers made up of the high-speed H8/300L CPU employing Renesas technology's original architecture as their cores, and the peripheral functions required to configure a system. The H8/300L CPU has an instruction set that is compatible with the H8/300 CPU. Below is a table listing the product specifications for each group.
H8/3802 Group Item ZTAT Memory ROM RAM Operating 4.5 to 5.5 V voltage 2.7 to 5.5 V and operating 1.8 to 5.5 V frequency 2.7 to 3.6 V 1.8 to 3.6 V I/O ports Input Output I/O Timers Clock (timer A) Compare (timer F) AEC WDT WDT (discrete) SCI UART/Clock frequency 1 ch 1 ch 1 ch 16 k 1k 16 MHz 10 MHz 4 MHz -- -- 9 6 39 1 1 1 H8/38004 Group H8/38002S Group H8/38104 Group
Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM 8 k to 16 k 512 or 1 k 16 MHz 10 MHz 4 MHz -- -- 9 6 39 1 1 1 16 k/32 k 1k -- -- -- 10 MHz 4 MHz (2.2 V or more) 9 6 39 1 1 1 1 1 1 ch 1 ch 32 k 1k 16 MHz 16 MHz -- -- -- 9 5 39 1 1 1 8 k to 16 k 512 k -- -- -- 10 MHz 4 MHz 9 6 39 1 1 1 1 1 1 ch 1 1 ch 16 k/32 k 1k 20 MHz 20 MHz -- -- -- 9 5 39 1 1 1 8 k to 32 k 512 or 1 k 20 MHz 20 MHz -- -- -- 9 5 39 1 1 1
A-D (resolution x input channels) LCD seg com External interrupt (internal wakeup) POR (power-on reset) LVD Package
10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 25 4 11(8) -- -- FP-64A FP-64E DP-64S 25 4 11(8) -- -- FP-64A FP-64E DP-64S die die 25 4 11(8) -- -- FP-64A FP-64E 25 4 11(8) -- -- FP-64A FP-64E 25 4 11(8) -- -- FP-64A FP-64K* 25 4 11(8) 1 1 FP-64A FP-64E 25 4 11(8) 1 1 FP-64A FP-64E
Operating temperature
Standard specifications: -20 to 75C, WTR: -40 to 85C
Note: * Under development. Rev. 6.00 Mar 15, 2005 page v of l
Target Users: This manual was written for users who will be using the H8/3802 Group, H8/38004 Group, H8/38002S Group, and H8/38104 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/3802 Group, H8/38004 Group, H8/38002S Group, and H8/38104 Group to the target users. Refer to the H8/300L Series Programming Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8/300L Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 14, List of Registers. Example: Bit order: The MSB is on the left and the LSB is on the right.
Notes: The following limitations apply to H8/38004, H8/38002, H8/38104, and H8/38102 programming and debugging when the on-chip emulator is used. 1. Pin P95 is not available because it is used exclusively by the on-chip emulator. 2. Pins P33, P34, and P35 are unavailable for use. In order to use these pins additional hardware must be mounted on the user board. 3. The address range H'7000 to H'7FFF is used by the on-chip emulator and is unavailable to the user. 4. The address range H'F780 to H'FB7F must not be accessed under any circumstances. 5. When the on-chip emulator is being used, pin P95 is I/O, pins P33 and P34 are input, and pin P35 is output. 6. When using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an external clock should be supplied to pin OSC1, even if the on-chip oscillator of the H8/38104 Group is selected. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/
Rev. 6.00 Mar 15, 2005 page vi of l
H8/3802 Group, H8/38004 Group, H8/38002S Group, H8/38104 Group manuals:
Document Title H8/3802 Group, H8/38004 Group, H8/38002S Group, H8/38104 Group Hardware Manual H8/300L Series Programming Manual Document No. This manual ADE-602-040
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop, Highperformance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual Document No. REJ10B0058-0100H (ADE-702-247) ADE-702-282 ADE-702-231 ADE-702-201
Application notes:
Document Title Single Power Supply F-ZTAT
TM
Document No. On-Board Programming ADE-502-055
Rev. 6.00 Mar 15, 2005 page vii of l
Rev. 6.00 Mar 15, 2005 page viii of l
Main Revisions and Additions in this Edition
Item All Preface v Page Revisions (See Manual for Details) H8/38002S added Table amended
H8/3802 Group Item ZTAT Memory ROM RAM Operating 4.5 to 5.5 V voltage 2.7 to 5.5 V and operating 1.8 to 5.5 V frequency 2.7 to 3.6 V 1.8 to 3.6 V I/O ports Input Output I/O Timers Clock (timer A) Compare (timer F) AEC WDT WDT (discrete) SCI UART/Clock frequency 1 ch 1 ch 1 ch 16 k 1k 16 MHz 10 MHz 4 MHz -- -- 9 6 39 1 1 1 H8/38004 Group H8/38002S Group H8/38104 Group Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM 8 k to 16 k 512 or 1 k 16 MHz 10 MHz 4 MHz -- -- 9 6 39 1 1 1 16 k/32 k 1k -- -- -- 10 MHz 4 MHz (2.2 V or more) 9 6 39 1 1 1 1 1 1 ch 1 ch 32 k 1k 16 MHz 16 MHz -- -- -- 9 5 39 1 1 1 8 k to 16 k 512 k -- -- -- 10 MHz 4 MHz 9 6 39 1 1 1 1 1 1 ch 1 1 ch 16 k/32 k 1k 20 MHz 20 MHz -- -- -- 9 5 39 1 1 1 8 k to 32 k 512 or 1 k 20 MHz 20 MHz -- -- -- 9 5 39 1 1 1
A-D (resolution x input input channels) LCD seg com External interrupt (internal wakeup) POR power-on ( reset) LVD Package
10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 10 bit x 4 ch 25 4 11(8) -- -- FP-64A FP-64E DP-64S 25 4 11(8) -- -- FP-64A FP-64E DP-64S die die 25 4 11(8) -- -- FP-64A FP-64E 25 4 11(8) -- -- FP-64A FP-64E 25 4 11(8) -- -- FP-64A FP-64K* 25 4 11(8) 1 1 FP-64A FP-64E 25 4 11(8) 1 1 FP-64A FP-64E
Operating temperature
Standard specifications: -20 to 75 C, WTR: -40 to 85 C
Note: * Under development.
Rev. 6.00 Mar 15, 2005 page ix of l
Item 1.1 Features
Page 1 to 3
Revisions (See Manual for Details) Description amended * Various peripheral functions Watchdog timer (WDT) (H8/38004, H8/38002S Group and H8/38104 Group only) * On-chip memory
Product Classification Mask ROM version H8/38002S H8/38001S H8/38000S H8/38104 H8/38103 H8/38102 H8/38101 H8/38100 Model HD64338002S HD64338001S HD64338000S HD64338104 HD64338103 HD64338102 HD64338101 HD64338100 ROM 16 kbytes 12 kbytes 8 kbytes 32 kbytes 24 kbytes 16 kbytes 12 kbytes 8 kbytes RAM 512 bytes 512 bytes 512 bytes 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes
* Compact package
Package QFP-64 LQFP-64 LQFP-64 DP-64S Die Code FP-64A FP-64E FP-64K* DP-64S
Body Size 14.0 x 14.0 mm 10.0 x 10.0 mm 17.0 x 57.6 mm
Pin Pitch 0.8 mm 0.5 mm 0.5 mm 1.0 mm
10.0 x 10.0 mm
Note added Note: * Under development. The package dimensions of the FP-64K and FP-64E differ. For details, see appendix E, Package Dimensions.
Rev. 6.00 Mar 15, 2005 page x of l
Item 1.2 Internal Block Diagram Figure 1.1 Internal Block Diagram of H8/3802 Group
Page 4
Revisions (See Manual for Details) Figure amended
x1 x2
Subclock oscillator
H8/300L CPU
Vss Vss = AVss Vcc RES TEST PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC
OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16
System clock oscillator
RAM
Port 3
Asynchronous event counter (AEC)
Port 4
Port 8
Timer A
Port 9
ROM
Port A
P95 P94 P93 P92 P91/PWM2 P90/PWM1
P80/SEG25
Port 5
10-bit PWM1 Timer F 10-bit PWM2
LCD power supply
P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0
Port 6
RAM
AVcc
10-bit A/D converter
Rev. 6.00 Mar 15, 2005 page xi of l
Port B
LCD controller/driver
Port 7
Item 1.2 Internal Block Diagram Figure 1.2 Internal Block Diagram of H8/38004 Group
Page 5
Revisions (See Manual for Details) Figure amended
x1 x2
Subclock oscillator
H8/300L CPU
Vss Vss = AVss Vcc RES TEST PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC
OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16
System clock oscillator
RAM
Port 3
ROM
Asynchronous event counter (AEC) Timer A
Port A
Port 4
P95 P94 P93 P92 P91/PWM2 P90/PWM1
Port 8
Port 9
P80/SEG25
Port 5
10-bit PWM1 Timer F 10-bit PWM2
P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0
WDT
Port 6
SCI3
LCD controller/driver
AVcc
10-bit A/D converter
Rev. 6.00 Mar 15, 2005 page xii of l
Port B
LCD power supply
Port 7
Item 1.2 Internal Block Diagram Figure 1.3 Internal Block Diagram of H8/38104 Group
Page 6
Revisions (See Manual for Details) Figure amended
x1 x2 CVcc Vss Vss = AVss Vcc RES TEST PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC
Subclock oscillator
H8/300L CPU
OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16
System clock oscillator
RAM
Port 3
ROM
Port 4
Port 8
Timer A
Power-on reset and low-voltage detection circuit
Port 9
Asynchronous event counter (AEC)
Port A
P95 P93/Vref P92 P91/PWM2 P90/PWM1
P80/SEG25
Port 5
10-bit PWM1 Timer F 10-bit PWM2
P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1/extU PB0/AN0/extD
WDT
Port 6
SCI3
LCD controller/driver
AVcc
10-bit A/D converter
1.3 Pin Arrangement Figure 1.4 Pin Arrangement of H8/3802, H8/38004 and H8/38002S Group (FP64A, FP-64E, FP-64K) 1.4 Pin Functions Table 1.4 Pin Functions
7
Title and figure amended FP-64A, FP-64E, FP-64K (Top view)
19 to 22
Table amended
Pin No. FP-64A, FP-64E, FP-64K 2 3 Pad Pad No.*1*3 No.*2 2 3 2 3
Type Clock pins
Symbol X1 X2
DP-64S 10 11
I/O Input Output
Functions These pins connect to a 32.768or 38.4-kHz*5 crystal resonator for subclocks. See section 4, Clock Pulse Generators, for a typical connection.
Note added Note: 5. Does not apply to H8/38104 Group
Rev. 6.00 Mar 15, 2005 page xiii of l
Port B
LCD power supply
Port 7
Item 2.2 Address Space and Memory Map Figure 2.1(6) H8/38002, H8/38102 Memory Map Figure 2.1(7) H8/38002S Memory Map
Page 29
Revisions (See Manual for Details) Notes amended Note 1. This area is unavailable to the user.
30
Newly added
Figure 2.1(8) 31 H8/38001, H8/38001S, H8/38101 Memory Map 32 Figure 2.1(9) H8/38000, H8/38000S, H8/38100 Memory Map 3.2.4 Interrupt Request Register 1 (IRR1) 80
Title amended
Title amended
Table amended
Bit 7 Bit Name IRRTA Initial Value 0 R/W R/W * Description Timer A Interrupt Request Flag [Setting condition] When the timer A counter value overflows [Clearing condition] When IRRTA = 1, it is cleared by writing 0
3.5.3 Interrupt Request Flag Clearing Method 3.5.4 Notes on Rewriting Port Mode Registers 4.1 Features
89, 90
Replaced
90 to 92
Replaced
93
Description amended Figure 4.1 shows a block diagram of the clock pulse generators of the H8/3802, H8/38004 and H8/38002S Group.
Figure 4.1 Block Diagram of Clock Pulse Generators (H8/3802, H8/38004, H8/38002S Group)
Title amended
Rev. 6.00 Mar 15, 2005 page xiv of l
Item 4.3 System Clock Generator Figure 4.3 Block Diagram of System Clock Generator
Page 96
Revisions (See Manual for Details) Figure amended
OSC2
LPM OSC1
4.3.1 Connecting Crystal Resonator
Description amended Figure 4.4(1) shows a typical method of connecting a crystal oscillator to the H8/3802 Group, and figure 4.4(2) shows a typical method of connecting a crystal oscillator to the H8/38004, H8/38104 and H8/38002S Group. 97 Title amended
Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004, H8/38002S, H8/38104 Group) Table 4.1 Crystal Resonator Parameters
Table amended
Frequency (MHz) RS (max) C0 (max) 4.10 100 7 pF 4.193
Rev. 6.00 Mar 15, 2005 page xv of l
Item 4.3.2 Connecting Ceramic Resonator
Page 98
Revisions (See Manual for Details) Description amended Figure 4.6(1) shows a typical method of connecting a ceramic oscillator to the H8/3802 Group, and figure 4.6(2) shows a typical method of connecting a crystal oscillator to the H8/38004, H8/38002S and H8/38104 Group. Title amended Figure amended
Frequency 2.0 MHz Manufacturer Prodoct Name C1, C2 Recommendation Value
15 pF 20% 47 pF 20% 15 pF 20% 47 pF 20% 15 pF 20% 15 pF 20%
Figure 4.6(2) Typical Connection to Ceramic Resonator (H8/38004, H8/38002S, H8/38104 Group)
Murata Manufacturing Co., CSTCC2M00G53-B0 Ltd. CSTCC2M00G56-B0
CSTLS10M0G53-B0 CSTLS10M0G56-B0
10.0 MHz 16.0 MHz*1 20.0 MHz*2 Rf = 1 M 20%
CSTLS16M0X53-B0 CSTLS20M0X53-B0
Notes: Consult with the crystal resonator manufacturer to determine the circuit constants. 1. This does not apply to the H8/38004 and H8/38002S Group. 2. H8/38104 Group only.
4.4.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator Figure 4.9 Typical Connection to 32.768kHz/38.4-kHz Crystal Resonator
100
Figure amended C1 = C2 = 6 to 12.5 pF (typ.)
Figure 4.10 Equivalent 101 Circuit of 32.768kHz/38.4-kHz Crystal Resonator
Figure amended CO = 0.8 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz/38.4 kHz
4.6.3 Definition of 106, 107 Description amended Oscillation Stabilization Meanwhile, once the system clock has halted, a standby time Standby Time is necessary in order for the CPU and peripheral functions to operate normally. Oscillation stabilization standby time = oscillation stabilization time + standby time
1 = trc + (8 to 16,384 states) * ................. (1)
(to 131,072 states) *2 Notes: 1. H8/3802 Group, H8/38004 and H8/38002S Group 2. H8/38104 Group Rev. 6.00 Mar 15, 2005 page xvi of l
Item
Page
Revisions (See Manual for Details) Description amended resonator characteristics, Depending on the individual the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. Note: * This figure applies to the H8/3802, H8/38004 and H8/38002S Groups. The number of states on the H8/38104 Group is 8,192 or more.
4.6.4 Notes on Use of 107 Resonator
5.1.1 System Control Register 1 (SYSCR1) Table 5.1(1) Operating Frequency and Waiting Time (H8/3802 Group, H8/38004 Group, H8/38002S Group) 5.2 Mode Transitions and States of LSI Figure 5.1 Mode Transition Diagram
111
Title amended
117
Note amended Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupts are enabled. Notes amended Notes: 8. On the H8/38104 Group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004, H8/38002S Group, operates when w/32 is selected as the internal clock; otherwise stops and stands by. 9. On the H8/38104 Group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004, H8/38002S Group, stops and stands by. 10. On the H8/38104 Group, operates only when the onchip oscillator is selected; other-wise stops and stands by. On the H8/38004, H8/38002S Group, stops and stands by.
120 Table 5.3 Internal State in Each Operating Mode
Rev. 6.00 Mar 15, 2005 page xvii of l
Item Section 6 ROM
Page 131
Revisions (See Manual for Details) Description amended The H8/3802 has 16 kbytes of the on-chip mask ROM, the H8/3801 has 12 kbytes, and the H8/3800 has 8 kbytes. The H8/38004 and H8/38104 have 32 kbytes of the on-chip mask ROM, the H8/38003 and H8/38103 have 24 kbytes, the H8/38002, H8/38002S and H8/38102 have 16 kbytes, the H8/38001, H8/38001S and H8/38101 have 12 kbytes, and the H8/38000, H8/38000S and H8/38100 have 8 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing highspeed two-state access for both byte data and word data.
6.7.1 Boot Mode Table 6.7 Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible (fOSC) Section 7 RAM
151
Table amended
Product Group H8/38104F Group Host Bit Rate 19,200 bps 9,600 bps 4,800 bps 2,400 bps 1,200 bps Oscillation Frequency Range of LSI (fOSC) 16 to 20 MHz 8 to 20 MHz 4 to 20 MHz 2 to 20 MHz 2 to 20 MHz
175
Table amended
Product Classification Mask ROM version H8/38002S H8/38001S H8/38000S RAM Size 512 bytes 512 bytes 512 bytes RAM Address H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F
Section 8 I/O Ports Table 8.1 Port Functions
178
Notes amended Notes: 2. Implemented on H8/3802 Group only. Standard highvoltage port on H8/38104 Group, H8/38002S Group and H8/38004 Group. 4. Implemented on H8/3802 Group only. Input port on H8/38004 Group, H8/38002S Group and H8/38104 Group.
8.1.5 Port Mode Register 2 (PMR2)
183
Table amended
Bit 2 Bit Name WDCKS Initial Value 0 R/W R/W Description Watchdog Timer Source Clock Select This bit selects the input clock for the watchdog timer. Note that this bit is implemented differently on the H8/38004, H8/38002S Group and on H8/38104 Group. H8/38004, H8/38002S Group: 0: /8,192 1: w/32 H8/38104 Group: 0: Clock specified by timer mode register W (TMW) 1: w/32 Note: This bit is reserved and only 0 can be written in the H8/3802 Group.
Rev. 6.00 Mar 15, 2005 page xviii of l
Item 8.2.3 Serial Port Control Register (SPCR)
Page 188
Revisions (See Manual for Details) Table amended Bit 3 Description TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 pin output data is inverted. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted 2 RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 pin input data is inverted. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted
8.7 Port 9
202
Description amended Port 9 is a dedicated current port for NMOS output that also functions as a PWM output pin.
8.7.2 Port Mode Register 9 (PMR9)
204
Table amended
Bit 3 Bit Name PIOFF Initial Value 0 R/W R/W Description P92 to P90 Step-Up Circuit Control This bit turns on and off the P92 to P90 step-up circuit. 0: Step-up circuit of large-current port is turned on 1: Step-up circuit of large-current port is turned off Note: This bit is valid in the H8/3802 Group only. It functions as a readable/writable reserved bit in versions other than the H8/3802 Group.
8.7.3 Pin Functions * P93/Vref
205
Description amended As shown below, switching is performed based on the setting of VREFSEL in LVDSR. Note that this function is implemented on the H8/38104 Group only. The Vref pin is the input pin for the LVD's external reference voltage. VREFSEL Pin Function 0 P93 output pin 1 Vref input pin
8.9.2 Port Mode Register B (PMRB)
209
Note deleted
Rev. 6.00 Mar 15, 2005 page xix of l
Item 9.1 Overview
Page 213
Revisions (See Manual for Details) Description amended The H8/3802 Group provides three timers: timer A, timer F, and asynchronous event counter. The H8/38004 Group, H8/38002S Group and H8/38104 Group provide four timers: timer A, timer F, asynchronous event counter, and watchdog timer.
Table 9.1 Timer Functions
214
Table and note amended
Name Watchdog timer* Functions * Internal Clock Event Input Waveform Pin Output Pin - - Remarks H8/38004, H8/38002S Group H8/38104 Group /8192, W /32 Generates a reset signal by overflow of 8-bit counter /64 to /8192 w/32 On-chip oscillator
Note: * The watchdog timer functions differently on the H8/38004, H8/38002S and H8/38104 Group. See section 9.5, Watchdog Timer, for details. 9.2.3 Operation 218 Description amended Clock Time Base Operation: When bit TMA3 in TMA is set to 1, the timer A functions as a clock-timer base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00. 9.3.4 CPU Interface 225 Description amended When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be transferred correctly if only the upper byte or only the lower byte is accessed. Access must be performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte. 9.3.5 Operation Timer F Operation * Operation in 16-bit timer mode 228 Description amended When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit timer. The timer F operating clock can be selected from three internal clocks output by prescaler S by means of bits CKSL2 to CKSL0 in TCRF.
Rev. 6.00 Mar 15, 2005 page xx of l
Item 9.4.6 Usage Notes
Page
Revisions (See Manual for Details) 2. The maximum clock frequency that may be input to the AEVH and AEVL pins is 16 MHz*1. Furthermore, the clock high width and low width should be half or more the OSC clock cycle time. The duty ratio does not matter as long as the high width and low width satisfy the minimum requirement.
Maximum Clock Frequency Input to AEVH/AEVL Pin (W/2) 1000 kHz (W/4) 500 kHz (W/8) 250 kHz Notes: 1. Up to 10 MHz in the H8/38004, H8/38002S Group. 2. Does not apply to H8/38104 Group.
248, 249 Description amended
Mode Watch, subactive, subsleep, standby W = 32.768 kHz or 38.4 kHz*
2
9.5 Watchdog Timer
250
Description amended However, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the implementation differs in the H8/38004, H8/38002S Group and the H8/38104 Group.
9.5.1 Features
Description amended * Selectable from two counter input clocks (H8/38004, H8/38002S Group).
Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004, H8/38002S Group) 9.5.2 Register Descriptions Timer Control/Status Register W (TCSRW) 9.5.3 Operation 254 253
Title amended
Notes amended Notes: 2.Initial value 0 on H8/38004, H8/38002S Group and 1 on H8/38104 Group. 3.On reset, cleared to 0 on H8/38004, H8/38002S Group and set to 1 on H8/38104 Group. Description amended The input clock is selected by the WDCKS bit in the port mode register 2 (PMR2)*: On the H8/38004, H8/38002S Group, /8192 is selected when the WDCKS bit is cleared to 0, and w/32 when set to 1.
Rev. 6.00 Mar 15, 2005 page xxi of l
Item
Page
Revisions (See Manual for Details) Description amended Tables 9.8(1) and 9.8(2) summarize the operating states of the watchdog timer for the H8/38004, H8/38002S Group and H8/38104 Group, respectively. Title amended
9.5.4 Operating States 256 of Watchdog Timer
Table 9.8(1) Operating States of Watchdog Timer (H8/38004, H8/38002S Group) 10.3.8 Bit Rate Register (BRR) 269
Description amended The values are shown in table 10.5
N=
.
-1
32 * 2 2n * B
Error (%) =
B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 10.2) R (bit rate in left-hand column in table 10.2)
* 100
Legend:
B: N:
:
n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.3.)
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
271
Table amended
10 MHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 3 3 3 3 3 3 3 2 2 0 0 N 43 32 23 19 15 7 3 1 0 1 0 9 7 Error (%) 0.88 -1.36 1.73 -2.34 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73
Rev. 6.00 Mar 15, 2005 page xxii of l
Item 10.3.8 Bit Rate Register (BRR) Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Page 272
Revisions (See Manual for Details) Table amended
Setting OSC (MHz) 0.0384* 2 2.4576 4 10 16 20
(MHz)
Maximum Bit Rate (bit/s) 600 31250 38400 62500 156250 250000 312500
n 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0
0.0192 1 1.2288 2 5 8 10
Table 10.5 BRR 273 Settings for Various Bit Rates (Clocked Synchronous Mode) (2)
Table amended
Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 10 MHz n 0 2 0 0 0 0 0 0 0 0 0 0 0 -- N 12499 624 8332 4999 2499 999 499 249 99 49 24 9 4 -- Error (%) 0 0 0 0 0 0 0 0 0 0 0 0 0 --
Note added
Note: The value set in BRR is given by the following formula:
N= 8 * 22n * B -1
B: N: : n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.6.)
Rev. 6.00 Mar 15, 2005 page xxiii of l
Item 10.3.9 Serial Port Control Register (SPCR)
Page 274
Revisions (See Manual for Details) Table amended Bit 3 Description TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 pin output data is inverted. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted 2 RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 pin input data is inverted. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted
10.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
291
Figure amended
Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read
1 frame
RXI interrupt request generated
ERI interrupt request generated by overrun error Overrun error processing
RDR data has not been read (RDRF = 1)
10.7 Interrupts Table 10.11 SCI3 Interrupt Requests
301
Table and description amended
Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, or PER in SSR Enable Bit RIE TIE TEIE RIE
Each interrupt request can be enabled or disabled by means of bits TIE, RIE and TEIE in SCR3. Table 10.12 Transmit/Receive Interrupts 302 Table amended Flag and Enable Bit Title and description amended When implementing serial communication interface 3 in asynchronous mode on the H8/38104 Group, the system clock oscillator must be used. The on-chip oscillator should not be used in this case.
10.8.10 Oscillator Use 307 with Serial Communication Interface 3 in Asynchronous Mode (H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page xxiv of l
Item Section 11 10-Bit PWM 11.1 Features
Page 309
Revisions (See Manual for Details) Description amended Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/3802 Group, H8/38004 Group and H8/38002S Group. Description amended * On the H8/38104 Group it is possible to select between two types of PWM output: pulse-division 10-bit PWM and event counter PWM (PWM incorporating AEC). (The H8/3802 Group, H8/38004 Group and H8/38002S Group can only produce 10-bit PWM output.) Refer to section 9.4, Asynchronous Event Counter, for information on event counter PWM.
310 Figure 11.1(1) Block Diagram of 10-Bit PWM (H8/3802 Group, H8/38004 Group, H8/38002S Group) 11.2 Input/Output Pins 311 Table 11.1 Pin Configuration 11.3.1 PWM Control Register (PWCR) 11.4.1 Operation 312
Title amended
Note amended Note: * The event counter PWM output pin is valid on the H8/38104 Group only. Description amended On the H8/3802 Group, H8/38004 Group and H8/38002S Group, PWCR selects the conversion period.
315
Description amended 1. Set the PWM2 and/or PWM1 bits in port mode register 9 (PMR9) to 1 to set the P91/PWM2 pin or P90/PWM1 pin, or both, to function as PWM output pins.
12.1 Features
317
Description amended * Conversion time: at least 12.4 s per channel ( = 5 MHz operation)/6.2 s ( = 10 MHz operation)*
12.7.1 Permissible Signal Source Impedance
327
Description amended As a countermeasure, a large capacitance can be provided externally to the analog input pin. This will cause the actual input resistance to comprise only the internal input resistance of 10 k , allowing the signal source impedance to be ignored. This countermeasure has the disadvantage of creating a low-pass filter from the signal source impedance and capacitance, with the result that it may not be possible to follow analog signals having a large differential coefficient (e.g., 5 mV/s or greater) (see figure 12.7). ...
12.7.3 Additional Usage Notes
328
Title amended
Rev. 6.00 Mar 15, 2005 page xxv of l
Item 13.1 Features
Page 329
Revisions (See Manual for Details) Description amended * On-chip power supply split-resistance Removal of split-resistance can be controlled in software. Note that this capability is implemented in the H8/38104 Group only.
Figure 13.1(1) Block Diagram of LCD Controller/Driver (H8/3802 Group, H8/38004 Group, H8/38002S Group) 13.3.3 LCD Control Register 2 (LCR2)
330
Title amended
338
Note amended Note: * Applies to H8/38104 Group only. On the H8/3802 Group, H8/38004 Group or H8/38002S Group, these bits are reserved like bit 4.
17.1 Absolute Maximum Ratings of H8/3802 Group (ZTAT Version, Mask ROM Version) 17.2 Electrical Characteristics of H8/3802 Group (ZTAT Version, Mask ROM Version)
377
Title amended
378
Title amended
394 17.3 Absolute Maximum Ratings of H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version) 395 17.4 Electrical Characteristics of H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version)
Title amended
Title amended
Rev. 6.00 Mar 15, 2005 page xxvi of l
Item 17.4.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range (FZTAT Version)
Page 395
Revisions (See Manual for Details) Figure amended
10.0
fosc(MHz)
4.0 2.0 2.2 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
4 MHz specification 10 MHz specification
17.5 Absolute 416 Maximum Ratings of H8/38104 Group (F-ZTAT Version, Mask ROM Version) 17.6 Electrical 417 Characteristics of H8/38104 Group (F-ZTAT Version, Mask ROM Version) 17.6.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected)
Title amended
Title amended
Figure amended
20.0
fosc (MHz)
2.0 2.7 5.5 VCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Rev. 6.00 Mar 15, 2005 page xxvii of l
Item 17.6.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected)
Page 418
Revisions (See Manual for Details) Figure amended
10.0
(MHz)
1.0 2.7 5.5 VCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode (except CPU)
1250
(kHz)
15.625 2.7 5.5 VCC (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter)
(MHz)
1.0 2.7 5.5 AVCC (V)
Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected)
420
Figure amended
10.0
* Active (high-speed) mode * Sleep (high-speed) mode
Rev. 6.00 Mar 15, 2005 page xxviii of l
Item 17.6.2 DC Characteristics Table 17.15 DC Characteristics (4)
Page 424
Revisions (See Manual for Details) Table amended
Values Item Symbol Applicable Pins VCC Test Condition Active (high-speed) mode VCC = 5 V, fOSC = 2 MHz Min -- Typ 0.8 Max -- Unit mA Notes *1 *3 *4 Approx. max. value = 1.1 * Typ. -- 1.5 -- *2 *3 *4 Approx. max. value = 1.1 * Typ.
Active IOPE1 mode current consumption
Table 17.15 DC Characteristics (5)
428
Table amended
Values Item Symbol Applicable Pins Port 9 Test Condition Min Typ -- Max 15.0 Unit mA Notes
Allowable IOL output low current (per pin)
VCC = 4.0 V to 5.5 V --
Other than above
--
--
5.0
17.6.3 AC Characteristics Table 17.16 Control Signal Timing
430
Table amended
Item System clock oscillation frequency OSC clock ( cycle time
OSC)
Symbol fOSC
Applicable Pins OSC1, OSC2
Values Test Condition Min 2.0 On-chip oscillator selected 0.7 50.0 On-chip oscillator selected 500 20 20 -- -- Typ -- -- -- -- -- -- -- -- Max 20.0 2.0 500 1429 -- -- 5 5 ns ns ns ns ns Unit MHz
Reference Figure
*2 Figure 17.1
tOSC
OSC1, OSC2
External clock high tCPH width External clock low width External clock rise time External clock fall time tCPL tCPr tCPf
OSC1 OSC1 OSC1 OSC1
Figure 17.1 Figure 17.1 Figure 17.1 Figure 17.1
431 Table 17.17 Serial Interface (SCI3) Timing
Table amended
Item Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) Symbol tRXS tRXH Test Condition Values Min 150.0 150.0 Typ Max Unit -- -- -- -- ns ns Reference Figure Figure 17.5 Figure 17.5
17.6.4 A/D Converter Characteristics Table 17.18 A/D Converter Characteristics 17.6.9 Watchdog Timer Characteristics Table 17.27 Watchdog Timer Characteristics
432
Table amended
Item Conversion time Symbol Applicable Test Pins Condition Values Min 6.2 Typ -- Max 124 Unit s Reference Figure
440
Table amended
Item On-chip oscillator overflow time Symbol tOVF Applicable Pins Test Condition VCC = 5 V Rated Values Min 0.2 Typ 0.4 Max -- Unit s Note *
Rev. 6.00 Mar 15, 2005 page xxix of l
Item A.1 Instruction List Table A.1 Instruction Set
Page 455
Revisions (See Manual for Details) Notes amended (4) The number of states required for execution is 4n + 9 (n = value of R4L). In the H8/38004 Group, H8/38002S Group and H8/38104 Group, the number of states required for execution is 4n + 8.
B.7 Port 9 Block Diagrams Figure B.7(c) Port 9 Block Diagram (Pin P93, H8/38104 Group Only) B.9 Port B Block Diagrams Figure B.9(b) Port B Block Diagram (Pin PB0, H8/38104 Group Only) Figure B.9(c) Port B Block Diagram (Pin PB1, H8/38104 Group Only) Appendix D Product Code Lineup Table D.3 Product Code Lineup of H8/38002S Group Appendix E Package Dimensions
478
Newly added
481
Newly added
482
Newly added
487
Newly added
490
Description amended The package dimensions are shown in figure E.1 (FP-64A), figure E.2 (FP-64E), figure E.3 (FP-64K), and figure E.4 (DP64S).
Figure E.3 Package Dimensions (FP-64K)
492
Newly added
Rev. 6.00 Mar 15, 2005 page xxx of l
Contents
Section 1 Overview.............................................................................................................
1.1 1.2 1.3 1.4 Features............................................................................................................................. Internal Block Diagram..................................................................................................... Pin Arrangement ............................................................................................................... Pin Functions .................................................................................................................... 1 1 4 7 19
Section 2 CPU ...................................................................................................................... 23
2.1 2.2 2.3 Features............................................................................................................................. Address Space and Memory Map ..................................................................................... Register Configuration...................................................................................................... 2.3.1 General Registers................................................................................................. 2.3.2 Program Counter (PC) ......................................................................................... 2.3.3 Condition Code Register (CCR) .......................................................................... 2.3.4 Initial Register Values ......................................................................................... Data Formats..................................................................................................................... 2.4.1 General Register Data Formats............................................................................ 2.4.2 Memory Data Formats ......................................................................................... Instruction Set................................................................................................................... 2.5.1 Data Transfer Instructions ................................................................................... 2.5.2 Arithmetic Operations Instructions...................................................................... 2.5.3 Logic Operations Instructions.............................................................................. 2.5.4 Shift Instructions.................................................................................................. 2.5.5 Bit Manipulation Instructions .............................................................................. 2.5.6 Branch Instructions.............................................................................................. 2.5.7 System Control Instructions................................................................................. 2.5.8 Block Data Transfer Instructions ......................................................................... Addressing Modes and Effective Address ........................................................................ 2.6.1 Addressing Modes ............................................................................................... 2.6.2 Effective Address Calculation ............................................................................. Basic Bus Cycle ................................................................................................................ 2.7.1 Access to On-Chip Memory (RAM, ROM)......................................................... 2.7.2 On-Chip Peripheral Modules ............................................................................... CPU States ........................................................................................................................ Usage Notes ...................................................................................................................... 2.9.1 Notes on Data Access to Empty Areas ................................................................ 2.9.2 Access to Internal I/O Registers .......................................................................... 2.9.3 EEPMOV Instruction........................................................................................... 2.9.4 Bit Manipulation Instructions .............................................................................. 23 24 33 34 34 35 36 36 36 38 39 41 43 44 44 46 49 51 52 53 53 56 60 60 61 63 64 64 64 65 65
2.4
2.5
2.6
2.7
2.8 2.9
Rev. 6.00 Mar 15, 2005 page xxxi of l
Section 3 Exception Handling ......................................................................................... 73
3.1 3.2 Exception Sources and Vector Address ............................................................................ Register Descriptions........................................................................................................ 3.2.1 Interrupt Edge Select Register (IEGR) ................................................................ 3.2.2 Interrupt Enable Register 1 (IENR1) ................................................................... 3.2.3 Interrupt Enable Register 2 (IENR2) ................................................................... 3.2.4 Interrupt Request Register 1 (IRR1) .................................................................... 3.2.5 Interrupt Request Register 2 (IRR2) .................................................................... 3.2.6 Wakeup Interrupt Request Register (IWPR) ....................................................... 3.2.7 Wakeup Edge Select Register (WEGR) .............................................................. Reset Exception Handling................................................................................................. Interrupt Exception Handling ........................................................................................... 3.4.1 External Interrupts ............................................................................................... 3.4.2 Internal Interrupts ................................................................................................ 3.4.3 Interrupt Handling Sequence ............................................................................... 3.4.4 Interrupt Response Time...................................................................................... Usage Notes ...................................................................................................................... 3.5.1 Interrupts after Reset............................................................................................ 3.5.2 Notes on Stack Area Use ..................................................................................... 3.5.3 Interrupt Request Flag Clearing Method ............................................................. 3.5.4 Notes on Rewriting Port Mode Registers ............................................................ 75 77 77 78 79 80 81 82 83 83 84 84 85 86 87 89 89 89 89 90
3.3 3.4
3.5
Section 4 Clock Pulse Generators................................................................................... 93
4.1 4.2 4.3 Features............................................................................................................................. Register Description ......................................................................................................... System Clock Generator ................................................................................................... 4.3.1 Connecting Crystal Resonator ............................................................................. 4.3.2 Connecting Ceramic Resonator ........................................................................... 4.3.3 External Clock Input Method .............................................................................. 4.3.4 On-Chip Oscillator Selection Method (H8/38104 Group Only).......................... Subclock Generator .......................................................................................................... 4.4.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator ......................................... 4.4.2 Pin Connection when Not Using Subclock.......................................................... 4.4.3 External Clock Input............................................................................................ Prescalers .......................................................................................................................... 4.5.1 Prescaler S ........................................................................................................... 4.5.2 Prescaler W.......................................................................................................... Usage Notes ...................................................................................................................... 4.6.1 Note on Resonators.............................................................................................. 4.6.2 Notes on Board Design ........................................................................................ 4.6.3 Definition of Oscillation Stabilization Standby Time.......................................... 4.6.4 Notes on Use of Resonator .................................................................................. 93 95 96 96 98 99 99 100 100 101 101 102 102 102 102 102 104 105 107
4.4
4.5
4.6
Rev. 6.00 Mar 15, 2005 page xxxii of l
4.6.5
Notes on H8/38104 Group................................................................................... 108
Section 5 Power-Down Modes........................................................................................ 109
5.1 Register Descriptions........................................................................................................ 5.1.1 System Control Register 1 (SYSCR1) ................................................................. 5.1.2 System Control Register 2 (SYSCR2) ................................................................. 5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) .................................. Mode Transitions and States of LSI.................................................................................. 5.2.1 Sleep Mode .......................................................................................................... 5.2.2 Standby Mode...................................................................................................... 5.2.3 Watch Mode......................................................................................................... 5.2.4 Subsleep Mode..................................................................................................... 5.2.5 Subactive Mode ................................................................................................... 5.2.6 Active (Medium-Speed) Mode ............................................................................ Direct Transition ............................................................................................................... 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode........................................................................................ 5.3.2 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode ............................................................................................. 5.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode.............. 5.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ........ 5.3.5 Notes on External Input Signal Changes before/after Direct Transition.............. Module Standby Function................................................................................................. Usage Notes ...................................................................................................................... 5.5.1 Standby Mode Transition and Pin States ............................................................. 5.5.2 Notes on External Input Signal Changes before/after Standby Mode.................. 110 110 113 114 116 120 121 121 122 122 123 124 125 126 126 127 127 128 128 128 128
5.2
5.3
5.4 5.5
Section 6 ROM..................................................................................................................... 131
6.1 6.2 Block Diagram.................................................................................................................. H8/3802 PROM Mode...................................................................................................... 6.2.1 Setting to PROM Mode ....................................................................................... 6.2.2 Socket Adapter Pin Arrangement and Memory Map........................................... H8/3802 Programming...................................................................................................... 6.3.1 Writing and Verifying.......................................................................................... 6.3.2 Programming Precautions.................................................................................... Reliability of Programmed Data ....................................................................................... Overview of Flash Memory .............................................................................................. 6.5.1 Features................................................................................................................ 6.5.2 Block Diagram..................................................................................................... 6.5.3 Block Configuration ............................................................................................ Register Descriptions........................................................................................................ 6.6.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 131 132 132 132 135 135 139 140 141 141 142 143 144 145
6.3
6.4 6.5
6.6
Rev. 6.00 Mar 15, 2005 page xxxiii of l
6.6.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 6.6.3 Erase Block Register (EBR) ................................................................................ 6.6.4 Flash Memory Power Control Register (FLPWCR)............................................ 6.6.5 Flash Memory Enable Register (FENR).............................................................. 6.7 On-Board Programming Modes........................................................................................ 6.7.1 Boot Mode ........................................................................................................... 6.7.2 Programming/Erasing in User Program Mode..................................................... 6.7.3 Notes on On-Board Programming ....................................................................... 6.8 Flash Memory Programming/Erasing............................................................................... 6.8.1 Program/Program-Verify..................................................................................... 6.8.2 Erase/Erase-Verify............................................................................................... 6.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 6.9 Program/Erase Protection ................................................................................................. 6.9.1 Hardware Protection ............................................................................................ 6.9.2 Software Protection ............................................................................................. 6.9.3 Error Protection ................................................................................................... 6.10 Programmer Mode ............................................................................................................ 6.10.1 Socket Adapter .................................................................................................... 6.10.2 Programmer Mode Commands............................................................................ 6.10.3 Memory Read Mode ............................................................................................ 6.10.4 Auto-Program Mode............................................................................................ 6.10.5 Auto-Erase Mode................................................................................................. 6.10.6 Status Read Mode ................................................................................................ 6.10.7 Status Polling ....................................................................................................... 6.10.8 Programmer Mode Transition Time .................................................................... 6.10.9 Notes on Memory Programming ......................................................................... 6.11 Power-Down States for Flash Memory.............................................................................
146 146 147 147 148 148 151 152 153 153 157 157 159 159 159 159 160 160 160 164 167 169 170 172 173 173 174
Section 7 RAM..................................................................................................................... 175
7.1 Block Diagram.................................................................................................................. 176
Section 8 I/O Ports .............................................................................................................. 177
8.1 Port 3................................................................................................................................. 8.1.1 Port Data Register 3 (PDR3) ............................................................................... 8.1.2 Port Control Register 3 (PCR3) ........................................................................... 8.1.3 Port Pull-Up Control Register 3 (PUCR3)........................................................... 8.1.4 Port Mode Register 3 (PMR3) ............................................................................. 8.1.5 Port Mode Register 2 (PMR2) ............................................................................. 8.1.6 Pin Functions ....................................................................................................... 8.1.7 Input Pull-Up MOS.............................................................................................. Port 4................................................................................................................................. 8.2.1 Port Data Register 4 (PDR4) ............................................................................... 179 180 180 181 182 183 184 185 186 186
8.2
Rev. 6.00 Mar 15, 2005 page xxxiv of l
8.2.2 Port Control Register 4 (PCR4) ........................................................................... 8.2.3 Serial Port Control Register (SPCR).................................................................... 8.2.4 Pin Functions ....................................................................................................... 8.3 Port 5................................................................................................................................. 8.3.1 Port Data Register 5 (PDR5) ............................................................................... 8.3.2 Port Control Register 5 (PCR5) ........................................................................... 8.3.3 Port Pull-Up Control Register 5 (PUCR5)........................................................... 8.3.4 Port Mode Register 5 (PMR5) ............................................................................. 8.3.5 Pin Functions ....................................................................................................... 8.3.6 Input Pull-Up MOS.............................................................................................. 8.4 Port 6................................................................................................................................. 8.4.1 Port Data Register 6 (PDR6) ............................................................................... 8.4.2 Port Control Register 6 (PCR6) ........................................................................... 8.4.3 Port Pull-Up Control Register 6 (PUCR6)........................................................... 8.4.4 Pin Functions ....................................................................................................... 8.4.5 Input Pull-Up MOS.............................................................................................. 8.5 Port 7................................................................................................................................. 8.5.1 Port Data Register 7 (PDR7) ............................................................................... 8.5.2 Port Control Register 7 (PCR7) ........................................................................... 8.5.3 Pin Functions ....................................................................................................... 8.6 Port 8................................................................................................................................. 8.6.1 Port Data Register 8 (PDR8) ............................................................................... 8.6.2 Port Control Register 8 (PCR8) ........................................................................... 8.6.3 Pin Functions ....................................................................................................... 8.7 Port 9................................................................................................................................. 8.7.1 Port Data Register 9 (PDR9) ............................................................................... 8.7.2 Port Mode Register 9 (PMR9) ............................................................................. 8.7.3 Pin Functions ....................................................................................................... 8.8 Port A................................................................................................................................ 8.8.1 Port Data Register A (PDRA).............................................................................. 8.8.2 Port Control Register A (PCRA) ......................................................................... 8.8.3 Pin Functions ....................................................................................................... 8.9 Port B ................................................................................................................................ 8.9.1 Port Data Register B (PDRB) .............................................................................. 8.9.2 Port Mode Register B (PMRB)............................................................................ 8.9.3 Pin Functions ....................................................................................................... 8.10 Usage Notes ...................................................................................................................... 8.10.1 How to Handle Unused Pin .................................................................................
187 187 189 190 191 191 192 192 193 194 194 195 195 196 196 197 198 198 199 199 200 201 201 202 202 203 204 204 205 206 206 207 208 209 209 210 211 211
Section 9 Timers .................................................................................................................. 213
9.1 9.2 Overview........................................................................................................................... 213 Timer A............................................................................................................................. 215
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9.3
9.4
9.5
9.2.1 Features................................................................................................................ 9.2.2 Register Descriptions........................................................................................... 9.2.3 Operation ............................................................................................................. 9.2.4 Timer A Operating States .................................................................................... Timer F ............................................................................................................................. 9.3.1 Features................................................................................................................ 9.3.2 Input/Output Pins................................................................................................. 9.3.3 Register Descriptions........................................................................................... 9.3.4 CPU Interface ...................................................................................................... 9.3.5 Operation ............................................................................................................. 9.3.6 Timer F Operating States..................................................................................... 9.3.7 Usage Notes......................................................................................................... Asynchronous Event Counter (AEC)................................................................................ 9.4.1 Features................................................................................................................ 9.4.2 Input/Output Pins................................................................................................. 9.4.3 Register Descriptions........................................................................................... 9.4.4 Operation ............................................................................................................. 9.4.5 Operating States of Asynchronous Event Counter .............................................. 9.4.6 Usage Notes......................................................................................................... Watchdog Timer ............................................................................................................... 9.5.1 Features................................................................................................................ 9.5.2 Register Descriptions........................................................................................... 9.5.3 Operation ............................................................................................................. 9.5.4 Operating States of Watchdog Timer ..................................................................
215 216 218 218 219 219 221 221 225 227 230 230 234 234 236 236 243 248 248 250 250 251 254 256
Section 10 Serial Communication Interface 3 (SCI3) .............................................. 257 10.1 Features............................................................................................................................. 257 10.2 Input/Output Pins.............................................................................................................. 259 10.3 Register Descriptions........................................................................................................ 259 10.3.1 Receive Shift Register (RSR) .............................................................................. 259 10.3.2 Receive Data Register (RDR).............................................................................. 260 10.3.3 Transmit Shift Register (TSR)............................................................................. 260 10.3.4 Transmit Data Register (TDR) ............................................................................ 260 10.3.5 Serial Mode Register (SMR) ............................................................................... 261 10.3.6 Serial Control Register 3 (SCR3) ........................................................................ 264 10.3.7 Serial Status Register (SSR) ................................................................................ 266 10.3.8 Bit Rate Register (BRR) ...................................................................................... 269 10.3.9 Serial Port Control Register (SPCR).................................................................... 274 10.4 Operation in Asynchronous Mode .................................................................................... 275 10.4.1 Clock.................................................................................................................... 276 10.4.2 SCI3 Initialization................................................................................................ 280 10.4.3 Data Transmission ............................................................................................... 281
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10.4.4 Serial Data Reception .......................................................................................... 10.5 Operation in Clocked Synchronous Mode ........................................................................ 10.5.1 Clock.................................................................................................................... 10.5.2 SCI3 Initialization................................................................................................ 10.5.3 Serial Data Transmission ..................................................................................... 10.5.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 10.5.5 Simultaneous Serial Data Transmission and Reception....................................... 10.6 Multiprocessor Communication Function ........................................................................ 10.6.1 Multiprocessor Serial Data Transmission ............................................................ 10.6.2 Multiprocessor Serial Data Reception ................................................................. 10.7 Interrupts........................................................................................................................... 10.8 Usage Notes ...................................................................................................................... 10.8.1 Break Detection and Processing .......................................................................... 10.8.2 Mark State and Break Sending............................................................................. 10.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 10.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................ 10.8.5 Note on Switching SCK32 Function.................................................................... 10.8.6 Relation between Writing to TDR and Bit TDRE ............................................... 10.8.7 Relation between RDR Reading and bit RDRF................................................... 10.8.8 Transmit and Receive Operations when Making State Transition....................... 10.8.9 Setting in Subactive or Subsleep Mode ............................................................... 10.8.10 Oscillator Use with Serial Communications Interface 3 (H8/38104 Group only) .......................................................................................
283 287 287 287 288 291 293 295 297 298 301 303 303 303 304 304 305 306 306 307 307 307
Section 11 10-Bit PWM .................................................................................................... 309
11.1 Features............................................................................................................................. 309 11.2 Input/Output Pins.............................................................................................................. 311 11.3 Register Descriptions........................................................................................................ 312 11.3.1 PWM Control Register (PWCR) ......................................................................... 312 11.3.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 314 11.4 Operation .......................................................................................................................... 315 11.4.1 Operation ............................................................................................................. 315 11.4.2 PWM Operating States ........................................................................................ 316
Section 12 A/D Converter................................................................................................. 317
12.1 Features............................................................................................................................. 317 12.2 Input/Output Pins.............................................................................................................. 319 12.3 Register Descriptions........................................................................................................ 319 12.3.1 A/D Result Registers H and L (ADRRH and ADRRL)....................................... 319 12.3.2 A/D Mode Register (AMR) ................................................................................. 320
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12.3.3 A/D Start Register (ADSR) ................................................................................. 12.4 Operation .......................................................................................................................... 12.4.1 A/D Conversion ................................................................................................... 12.4.2 Operating States of A/D Converter...................................................................... 12.5 Example of Use................................................................................................................. 12.6 A/D Conversion Accuracy Definitions ............................................................................. 12.7 Usage Notes ...................................................................................................................... 12.7.1 Permissible Signal Source Impedance ................................................................. 12.7.2 Influences on Absolute Accuracy ........................................................................ 12.7.3 Additional Usage Notes.......................................................................................
321 321 321 322 322 325 327 327 327 327
Section 13 LCD Controller/Driver ................................................................................. 329
13.1 Features............................................................................................................................. 329 13.2 Input/Output Pins.............................................................................................................. 332 13.3 Register Descriptions........................................................................................................ 333 13.3.1 LCD Port Control Register (LPCR)..................................................................... 333 13.3.2 LCD Control Register (LCR) .............................................................................. 336 13.3.3 LCD Control Register 2 (LCR2) ......................................................................... 338 13.4 Operation .......................................................................................................................... 339 13.4.1 Settings up to LCD Display ................................................................................. 339 13.4.2 Relationship between LCD RAM and Display.................................................... 341 13.4.3 Operation in Power-Down Modes ....................................................................... 346 13.4.4 Boosting LCD Drive Power Supply..................................................................... 347
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)............................................................................................................................. 349
14.1 Features............................................................................................................................. 349 14.2 Register Descriptions........................................................................................................ 351 14.2.1 Low-Voltage Detection Control Register (LVDCR) ........................................... 351 14.2.2 Low-Voltage Detection Status Register (LVDSR) .............................................. 353 14.2.3 Low-Voltage Detection Counter (LVDCNT) ...................................................... 354 14.3 Operation .......................................................................................................................... 354 14.3.1 Power-On Reset Circuit....................................................................................... 354 14.3.2 Low-Voltage Detection Circuit ........................................................................... 355
Section 15 Power Supply Circuit (H8/38104 Group Only) .................................... 363
15.1 When Using Internal Power Supply Step-Down Circuit .................................................. 363 15.2 When Not Using Internal Power Supply Step-Down Circuit............................................ 364
Section 16 List of Registers.............................................................................................. 365
16.1 Register Addresses (Address Order)................................................................................. 366 16.2 Register Bits ..................................................................................................................... 370
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16.3 Register States in Each Operating Mode .......................................................................... 373
Section 17 Electrical Characteristics ............................................................................. 377
17.1 Absolute Maximum Ratings of H8/3802 Group (ZTAT Version, Mask ROM Version) ............................................................................. 17.2 Electrical Characteristics of H8/3802 Group (ZTAT Version, Mask ROM Version) ...... 17.2.1 Power Supply Voltage and Operating Ranges ..................................................... 17.2.2 DC Characteristics ............................................................................................... 17.2.3 AC Characteristics ............................................................................................... 17.2.4 A/D Converter Characteristics............................................................................. 17.2.5 LCD Characteristics............................................................................................. 17.3 Absolute Maximum Ratings of H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version)....... 17.4 Electrical Characteristics of H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version)....... 17.4.1 Power Supply Voltage and Operating Ranges ..................................................... 17.4.2 DC Characteristics ............................................................................................... 17.4.3 AC Characteristics ............................................................................................... 17.4.4 A/D Converter Characteristics............................................................................. 17.4.5 LCD Characteristics............................................................................................. 17.4.6 Flash Memory Characteristics ............................................................................. 17.5 Absolute Maximum Ratings of H8/38104 Group (F-ZTAT Version, Mask ROM Version) .......................................................................... 17.6 Electrical Characteristics of H8/38104 Group (F-ZTAT Version, Mask ROM Version) .......................................................................... 17.6.1 Power Supply Voltage and Operating Ranges ..................................................... 17.6.2 DC Characteristics ............................................................................................... 17.6.3 AC Characteristics ............................................................................................... 17.6.4 A/D Converter Characteristics............................................................................. 17.6.5 LCD Characteristics............................................................................................. 17.6.6 Flash Memory Characteristics ............................................................................. 17.6.7 Power Supply Voltage Detection Circuit Characteristics .................................... 17.6.8 Power-On Reset Circuit Characteristics .............................................................. 17.6.9 Watchdog Timer Characteristics.......................................................................... 17.7 Operation Timing.............................................................................................................. 17.8 Output Load Condition ..................................................................................................... 17.9 Resonator Equivalent Circuit............................................................................................ 17.10 Usage Note........................................................................................................................ 377 378 378 381 388 391 393 394 395 395 399 406 411 413 414 416 417 417 421 430 432 433 434 436 439 440 440 442 443 444
Appendix A Instruction Set .............................................................................................. 445
A.1 A.2 Instruction List.................................................................................................................. 445 Operation Code Map......................................................................................................... 456
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A.3
Number of Execution States ............................................................................................. 458
Appendix B I/O Port Block Diagrams .......................................................................... 465
B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 Port 3 Block Diagrams...................................................................................................... Port 4 Block Diagrams...................................................................................................... Port 5 Block Diagram ....................................................................................................... Port 6 Block Diagram ....................................................................................................... Port 7 Block Diagram ....................................................................................................... Port 8 Block Diagram ....................................................................................................... Port 9 Block Diagrams...................................................................................................... Port A Block Diagram ...................................................................................................... Port B Block Diagrams ..................................................................................................... 465 469 473 474 475 476 477 479 480
Appendix C Port States in Each Operating State ....................................................... 483 Appendix D Product Code Lineup ................................................................................. 484 Appendix E Package Dimensions................................................................................... 490 Appendix F Chip Form Specifications.......................................................................... 494 Appendix G Bonding Pad Form...................................................................................... 496 Appendix H Chip Tray Specifications .......................................................................... 497 Index
............................................................................................................................. 501
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Figures
Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3802 Group ....................................................... 4 Figure 1.2 Internal Block Diagram of H8/38004 Group ..................................................... 5 Figure 1.3 Internal Block Diagram of H8/38104 Group ..................................................... 6 Figure 1.4 Pin Arrangement of H8/3802 and H8/38004 Group (FP-64A, FP-64E)............ 7 Figure 1.5 Pin Arrangement of H8/3802 Group (DP-64S) ................................................. 8 Figure 1.6 Pin Arrangement of H8/38104 Group (FP-64A, FP-64E) ................................. 9 Figure 1.7 Pad Arrangement of HCD6433802, HCD6433801, and HCD6433800 (Top View)......................................................................................................... 10 Figure 1.8 Pad Arrangement of HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000 (Top View) .............................................. 13 Figure 1.9 Pad Arrangement of HCD64F38004 and HCD64F38002 (Top View).............. 16 Section 2 CPU Figure 2.1(1) H8/3802 Memory Map ...................................................................................... Figure 2.1(2) H8/3801 Memory Map ...................................................................................... Figure 2.1(3) H8/3800 Memory Map ...................................................................................... Figure 2.1(4) H8/38004, H8/38104 Memory Map .................................................................. Figure 2.1(5) H8/38003, H8/38103 Memory Map .................................................................. Figure 2.1(6) H8/38002, H8/38102 Memory Map .................................................................. Figure 2.1(7) H8/38001, H8/38101 Memory Map .................................................................. Figure 2.1(8) H8/38000, H8/38100 Memory Map .................................................................. Figure 2.2 CPU Registers.................................................................................................... Figure 2.3 Stack Pointer...................................................................................................... Figure 2.4 General Register Data Formats.......................................................................... Figure 2.5 Memory Data Formats ....................................................................................... Figure 2.6 Instruction Formats of Data Transfer Instructions ............................................. Figure 2.7 Instruction Formats of Arithmetic, Logic, and Shift Instructions ...................... Figure 2.8 Instruction Formats of Bit Manipulation Instructions........................................ Figure 2.9 Instruction Formats of Branch Instructions ....................................................... Figure 2.10 Instruction Formats of System Control Instructions .......................................... Figure 2.11 Instruction Format of Block Data Transfer Instructions .................................... Figure 2.12 On-Chip Memory Access Cycle ........................................................................ Figure 2.13 On-Chip Peripheral Module Access Cycle (2-State Access) ............................. Figure 2.14 On-Chip Peripheral Module Access Cycle (3-State Access) ............................. Figure 2.15 CPU Operation States ........................................................................................ Figure 2.16 State Transitions ................................................................................................ Figure 2.17 Example of Timer Configuration with Two Registers Allocated to Same Address ..............................................................................................................
24 25 26 27 28 29 30 31 32 33 36 37 41 44 47 49 50 51 58 59 60 61 62 63
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Section 3 Exception Handling Figure 3.1 Reset Sequence .................................................................................................. Figure 3.2 Stack Status after Exception Handling............................................................... Figure 3.3 Interrupt Sequence ............................................................................................. Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure..... Section 4 Clock Pulse Generators Figure 4.1 Block Diagram of Clock Pulse Generators (H8/3802, H8/38004 Group) ......... Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38104 Group) ......................... Figure 4.3 Block Diagram of System Clock Generator ...................................................... Figure 4.4(1) Typical Connection to Crystal Resonator (H8/3802 Group) ............................. Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004, H8/38104 Group).......... Figure 4.5 Equivalent Circuit of Crystal Resonator ............................................................ Figure 4.6(1) Typical Connection to Ceramic Resonator (H8/3802 Group) ........................... Figure 4.6(2) Typical Connection to Ceramic Resonator (H8/38004, H8/38104 Group)........ Figure 4.7 Example of External Clock Input ...................................................................... Figure 4.8 Block Diagram of Subclock Generator.............................................................. Figure 4.9 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator ...................... Figure 4.10 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator ........................ Figure 4.11 Pin Connection when Not Using Subclock........................................................ Figure 4.12 Pin Connection when Inputting External Clock................................................. Figure 4.13 Example of Crystal and Ceramic Resonator Arrangement ................................ Figure 4.14 Negative Resistor Measurement and Proposed Changes in Circuit................... Figure 4.15 Example of Incorrect Board Design .................................................................. Figure 4.16 Oscillation Stabilization Standby Time .............................................................
79 81 82 85
87 88 90 90 91 91 91 92 92 93 93 94 94 94 96 97 97 98
Section 5 Power-Down Modes Figure 5.1 Mode Transition Diagram.................................................................................. 107 Figure 5.2 Standby Mode Transition and Pin States ........................................................... 117 Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode.......................................................................... 118 Section 6 ROM Figure 6.1 Block Diagram of ROM (H8/3802)................................................................... Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101) ................................... Figure 6.3 H8/3802 Memory Map in PROM Mode............................................................ Figure 6.4 High-Speed, High-Reliability Programming Flowchart .................................... Figure 6.5 PROM Write/Verify Timing.............................................................................. Figure 6.6 Recommended Screening Procedure ................................................................. Figure 6.7 Block Diagram of Flash Memory ...................................................................... Figure 6.8(1) Block Configuration of 32-kbyte Flash Memory............................................... Figure 6.8(2) Block Configuration of 16-kbyte Flash Memory...............................................
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119 121 122 124 127 128 130 131 132
Figure 6.9 Figure 6.10 Figure 6.11 Figure 6.12(1) Figure 6.12(2) Figure 6.13 Figure 6.14 Figure 6.15 Figure 6.16 Figure 6.17 Figure 6.18 Figure 6.19 Figure 6.20
Programming/Erasing Flowchart Example in User Program Mode .................. Program/Program-Verify Flowchart.................................................................. Erase/Erase-Verify Flowchart............................................................................ Socket Adapter Pin Correspondence Diagram (H8/38004F, H8/38002F)......... Socket Adapter Pin Correspondence Diagram (H8/38104F, H8/38102F)......... Timing Waveforms for Memory Read after Command Write........................... Timing Waveforms in Transition from Memory Read Mode to Another Mode.................................................................................................... Timing Waveforms in and Enable State Read....................................... Timing Waveforms in and Clock System Read .................................... Timing Waveforms in Auto-Program Mode...................................................... Timing Waveforms in Auto-Erase Mode........................................................... Timing Waveforms in Status Read Mode.......................................................... Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence ...............................................................................
140 142 145 148 149 150 151 152 152 154 155 156 158
Section 7 RAM Figure 7.1 Block Diagram of RAM (H8/3802)................................................................... 162 Section 8 I/O Ports Figure 8.1 Port 3 Pin Configuration .................................................................................... Figure 8.2 Port 4 Pin Configuration .................................................................................... Figure 8.3 Input/Output Data Inversion Function ............................................................... Figure 8.4 Port 5 Pin Configuration .................................................................................... Figure 8.5 Port 6 Pin Configuration .................................................................................... Figure 8.6 Port 7 Pin Configuration .................................................................................... Figure 8.7 Port 8 Pin Configuration .................................................................................... Figure 8.8 Port 9 Pin Configuration .................................................................................... Figure 8.9 Port A Pin Configuration ................................................................................... Figure 8.10 Port B Pin Configuration ...................................................................................
Section 9 Timers Figure 9.1 Block Diagram of Timer A................................................................................ 200 Figure 9.2 Block Diagram of Timer F................................................................................. 204 Figure 9.3 Write Access to TCF (CPU TCF) ................................................................. 210 Figure 9.4 Read Access to TCF (TCF CPU).................................................................. 211 Figure 9.5 TMOFH/TMOFL Output Timing ...................................................................... 213 Figure 9.6 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid .................................................................................................................. 217 Figure 9.7 Block Diagram of Asynchronous Event Counter............................................... 219 Figure 9.8 Example of Software Processing when Using ECH and ECL as 16-Bit Event Counter ......................................................................................... 228
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EO EO
EC EC
165 172 173 176 180 184 186 188 190 192
Figure 9.9
Example of Software Processing when Using ECH and ECL as 8-Bit Event Counters ......................................................................................... Figure 9.10 Event Counter Operation Waveform ................................................................. Figure 9.11 Example of Clock Control Operation ................................................................ Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004 Group).................................... Figure 9.12(2) Block Diagram of Watchdog Timer (H8/38104 Group).................................... Figure 9.13 Example of Watchdog Timer Operation............................................................ Section 10 Serial Communication Interface 3 (SCI3) Figure 10.1 Block Diagram of SCI3 ..................................................................................... Figure 10.2 Data Format in Asynchronous Communication................................................. Figure 10.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ....... Figure 10.4 Sample SCI3 Initialization Flowchart................................................................ Figure 10.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)...................................................................... Figure 10.6 Sample Serial Transmission Flowchart (Asynchronous Mode)......................... Figure 10.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)...................................................................... Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)................ Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)................ Figure 10.9 Data Format in Clocked Synchronous Communication..................................... Figure 10.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode.. Figure 10.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)............. Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode ........... Figure 10.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode).................. Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode) ........................................................................... Figure 10.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ...................................... Figure 10.16 Sample Multiprocessor Serial Transmission Flowchart .................................... Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (1) .................................... Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (2) .................................... Figure 10.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .......................... Figure 10.19(a) RDRF Setting and RXI Interrupt ....................................................................... Figure 10.19(b) TDRE Setting and TXI Interrupt ....................................................................... Figure 10.19(c) TEND Setting and TEI Interrupt ....................................................................... Figure 10.20 Receive Data Sampling Timing in Asynchronous Mode................................... Figure 10.21 Relation between RDR Read Timing and Data .................................................
229 230 231 234 235 238
242 256 257 261 262 263 265 266 267 268 269 270 271 272 273 275 276 277 278 279 281 282 282 284 285
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Section 11 10-Bit PWM Figure 11.1(1) Block Diagram of 10-Bit PWM (H8/3802 Group, H8/38004 Group) ............... 287 Figure 11.1(2) Block Diagram of 10-Bit PWM (H8/38104 Group) .......................................... 288 Figure 11.2 Waveform Output by 10-Bit PWM.................................................................... 291 Section 12 A/D Converter Figure 12.1 Block Diagram of A/D Converter...................................................................... Figure 12.2 Example of A/D Conversion Operation............................................................. Figure 12.3 Flowchart of Procedure for Using A/D Converter (Polling by Software).......... Figure 12.4 Flowchart of Procedure for Using A/D Converter (Interrupts Used)................. Figure 12.5 A/D Conversion Accuracy Definitions (1) ........................................................ Figure 12.6 A/D Conversion Accuracy Definitions (2) ........................................................ Figure 12.7 Example of Analog Input Circuit....................................................................... Section 13 LCD Controller/Driver Figure 13.1(1) Block Diagram of LCD Controller/Driver (H8/3802 Group, H8/38004 Group) .................................................................. Figure 13.1(2) Block Diagram of LCD Controller/Driver (H8/38104 Group) .......................... Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty........................... Figure 13.3 LCD RAM Map (1/4 Duty) ............................................................................... Figure 13.4 LCD RAM Map (1/3 Duty) ............................................................................... Figure 13.5 LCD RAM Map (1/2 Duty) ............................................................................... Figure 13.6 LCD RAM Map (Static Mode) .......................................................................... Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform) .................................. Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)................................... Figure 13.9 Connection of External Split-Resistance ...........................................................
294 299 300 300 301 302 303
306 307 314 315 316 316 317 318 319 321
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only) Figure 14.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit ................................................................................................................ 324 Figure 14.2 Operational Timing of Power-On Reset Circuit ................................................ 328 Figure 14.3 Operational Timing of LVDR Circuit................................................................ 329 Figure 14.4 Operational Timing of LVDI Circuit ................................................................. 330 Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit (Using Pins Vref, extD, and extU)..................................................................... 331 Figure 14.6 LVD Function Usage Example Employing Pins Vref, extD, and extU ............. 332 Figure 14.7 Timing for Operation/Release of Low-Voltage Detection Circuit..................... 334 Section 15 Power Supply Circuit (H8/38104 Group Only) Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used............... 335 Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used........ 336
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Section 17 Electrical Characteristics Figure 17.1 Clock Input Timing............................................................................................ Low Width Timing .................................................................................... Figure 17.2 Figure 17.3 Input Timing ...................................................................................................... Figure 17.4 SCK3 Input Clock Timing................................................................................. Figure 17.5 SCI3 Input/Output Timing in Clocked Synchronous Mode .............................. Figure 17.6 Output Load Circuit........................................................................................... Figure 17.7 Resonator Equivalent Circuit............................................................................. Figure 17.8 Resonator Equivalent Circuit............................................................................. Appendices Figure B.1(a) Figure B.1(b) Figure B.1(c) Figure B.1(d) Figure B.2(a) Figure B.2(b) Figure B.2(c) Figure B.2(d) Figure B.3 Figure B.4 Figure B.5 Figure B.6 Figure B.7(a) Figure B.7(b) Figure B.8 Figure B.9 Figure E.1 Figure E.2 Figure E.3 Figure F.1 Figure F.2 Figure F.3 Figure G.1
408 408 408 409 409 409 410 410
Figure H.1 Figure H.2 Figure H.3
Port 3 Block Diagram (Pins P37 and P36)......................................................... Port 3 Block Diagram (Pin P35) ........................................................................ Port 3 Block Diagram (Pins P34 and P33)......................................................... Port 3 Block Diagram (Pins P32 and P31)......................................................... Port 4 Block Diagram (Pin P43) ........................................................................ Port 4 Block Diagram (Pin P42) ........................................................................ Port 4 Block Diagram (Pin P41) ........................................................................ Port 4 Block Diagram (Pin P40) ........................................................................ Port 5 Block Diagram ........................................................................................ Port 6 Block Diagram ........................................................................................ Port 7 Block Diagram ........................................................................................ Port 8 Block Diagram (Pin P80) ........................................................................ Port 9 Block Diagram (Pins P91 and P90)......................................................... Port 9 Block Diagram (Pins P95 to P92) ........................................................... Port A Block Diagram ....................................................................................... Port B Block Diagram........................................................................................ Package Dimensions (FP-64A).......................................................................... Package Dimensions (FP-64E) .......................................................................... Package Dimensions (DP-64S).......................................................................... Cross-Sectional View of Chip (HCD6433802, HCD6433801, and HCD6433800)........................................... Cross-Sectional View of Chip (HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000) ...................................... Cross-Sectional View of Chip (HCD64F38004 and HCD64F38002) ............... Bonding Pad Form (HCD6433802, HCD6433801, HCD6433800, HCD64338004, HCD64338003, HCD64338002, HCD64338001, HCD64338000, HCD64F38004, and HCD64F38002)...................................... Chip Tray Specifications (HCD6433802, HCD6433801, and HCD6433800) .. Chip Tray Specifications (HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000)................................................................. Chip Tray Specifications (HCD64F38004 and HCD64F38002) .......................
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SER
433 434 434 435 435 436 437 438 439 440 441 442 442 443 443 444 451 452 453 454 454 455
456 457 458 459
Tables
Section 1 Overview Table 1.1 Pad Coordinate of HCD6433802, HCD6433801, and HCD6433800 .................... Table 1.2 Pad Coordinate of HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000 ...................................................................... Table 1.3 Pad Coordinate of HCD64F38004 and HCD64F38002 ......................................... Table 1.4 Pin Functions.......................................................................................................... Section 2 CPU Table 2.1 Instruction Set ........................................................................................................ Table 2.2 Operation Notation................................................................................................. Table 2.3 Data Transfer Instructions...................................................................................... Table 2.4 Arithmetic Operations Instructions ........................................................................ Table 2.5 Logic Operations Instructions ................................................................................ Table 2.6 Shift Instructions .................................................................................................... Table 2.7 Bit Manipulation Instructions (1)........................................................................... Table 2.7 Bit Manipulation Instructions (2)........................................................................... Table 2.8 Branch Instructions ................................................................................................ Table 2.9 System Control Instructions ................................................................................... Table 2.10 Block Data Transfer Instructions ........................................................................... Table 2.11 Addressing Modes.................................................................................................. Table 2.12 Effective Address Calculation................................................................................ Table 2.13 Registers with Shared Addresses ........................................................................... Table 2.14 Registers with Write-Only Bits .............................................................................. 11 14 17 19
38 39 40 42 43 43 45 46 48 50 51 52 55 68 68
Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address ................................................................. 71 Table 3.2 Interrupt Wait States .............................................................................................. 81 Table 3.3 Conditions under which Interrupt Request Flag is Set to 1.................................... 83 Section 4 Clock Pulse Generators Table 4.1 Crystal Resonator Parameters ................................................................................ 91 Table 4.2 System Clock Oscillator and On-Chip Oscillator Selection Methods.................... 93 Section 5 Power-Down Modes Table 5.1(1) Operating Frequency and Waiting Time (H8/3802 Group, H8/38004 Group) ...... Table 5.1(2) Operating Frequency and Waiting Time (H8/38104 Group) ................................. Table 5.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ....... Table 5.3 Internal State in Each Operating Mode ..................................................................
103 103 108 109
Rev. 6.00 Mar 15, 2005 page xlvii of l
Section 6 ROM Table 6.1 Setting to PROM Mode.......................................................................................... Table 6.2 Mode Selection in PROM Mode (H8/3802) .......................................................... Table 6.3 DC Characteristics ................................................................................................. Table 6.4 AC Characteristics ................................................................................................. Table 6.5 Setting Programming Modes.................................................................................. Table 6.6 Boot Mode Operation............................................................................................. Table 6.7 Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible (fOSC) ........................................................................................................ Table 6.8 Reprogram Data Computation Table ..................................................................... Table 6.9 Additional-Program Data Computation Table ....................................................... Table 6.10 Programming Time ................................................................................................ Table 6.11 Command Sequence in Programmer Mode............................................................ Table 6.12 AC Characteristics in Transition to Memory Read Mode...................................... Table 6.13 AC Characteristics in Transition from Memory Read Mode to Another Mode..... Table 6.14 AC Characteristics in Memory Read Mode ........................................................... Table 6.15 AC Characteristics in Auto-Program Mode ........................................................... Table 6.16 AC Characteristics in Auto-Erase Mode................................................................ Table 6.17 AC Characteristics in Status Read Mode ............................................................... Table 6.18 Return Codes in Status Read Mode........................................................................ Table 6.19 Status Polling Output ............................................................................................. Table 6.20 Stipulated Transition Times to Command Wait State............................................ Table 6.21 Flash Memory Operating States.............................................................................
120 123 125 126 136 138 139 143 143 143 147 150 151 151 153 155 156 157 157 158 159
Section 8 I/O Ports Table 8.1 Port Functions ........................................................................................................ 163 Section 9 Timers Table 9.1 Timer Functions ..................................................................................................... Table 9.2 Timer A Operating States....................................................................................... Table 9.3 Pin Configuration................................................................................................... Table 9.4 Timer F Operating States ....................................................................................... Table 9.5 Pin Configuration................................................................................................... Table 9.6 Examples of Event Counter PWM Operation ........................................................ Table 9.7 Operating States of Asynchronous Event Counter................................................. Table 9.8(1) Operating States of Watchdog Timer (H8/38004 Group) ...................................... Table 9.8(2) Operating States of Watchdog Timer (H8/38104 Group) ......................................
198 202 204 214 220 231 232 239 239
Section 10 Serial Communication Interface 3 (SCI3) Table 10.1 Pin Configuration................................................................................................... 243 Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ....... 251 Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ....... 252
Rev. 6.00 Mar 15, 2005 page xlviii of l
Table 10.3 Table 10.4 Table 10.5 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12
Relation between n and Clock................................................................................ Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) ................ BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) ................ Relation between n and Clock................................................................................ Data Transfer Formats (Asynchronous Mode)....................................................... SMR Settings and Corresponding Data Transfer Formats ..................................... SMR and SCR3 Settings and Clock Source Selection ........................................... SSR Status Flags and Receive Data Handling ....................................................... SCI3 Interrupt Requests ......................................................................................... Transmit/Receive Interrupts...................................................................................
252 253 253 254 255 258 259 260 265 280 281
Section 11 10-Bit PWM Table 11.1 Pin Configuration................................................................................................... 288 Table 11.2 PWM Operating States........................................................................................... 292 Section 12 A/D Converter Table 12.1 Pin Configuration................................................................................................... 295 Table 12.2 Operating States of A/D Converter ........................................................................ 297 Section 13 LCD Controller/Driver Table 13.1 Pin Configuration................................................................................................... Table 13.2 Duty Cycle and Common Function Selection ........................................................ Table 13.3 Segment Driver Selection ...................................................................................... Table 13.4 Frame Frequency Selection.................................................................................... Table 13.5 Output Levels ......................................................................................................... Table 13.6 Power-Down Modes and Display Operation..........................................................
308 310 310 312 320 321
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only) Table 14.1 LVDCR Settings and Select Functions .................................................................. 326 Section 17 Electrical Characteristics Table 17.1 Absolute Maximum Ratings................................................................................... Table 17.2 DC Characteristics (1)............................................................................................ Table 17.2 DC Characteristics (2)............................................................................................ Table 17.2 DC Characteristics (3)............................................................................................ Table 17.2 DC Characteristics (4)............................................................................................ Table 17.2 DC Characteristics (5)............................................................................................ Table 17.2 DC Characteristics (6)............................................................................................ Table 17.3 Control Signal Timing............................................................................................ Table 17.4 Serial Interface (SCI3) Timing............................................................................... Table 17.5 A/D Converter Characteristics ...............................................................................
347 351 352 353 354 355 356 358 360 360
Rev. 6.00 Mar 15, 2005 page xlix of l
Table 17.6 Table 17.7 Table 17.8 Table 17.9 Table 17.10 Table 17.11 Table 17.12 Table 17.13 Table 17.14 Table 17.15 Table 17.15 Table 17.15 Table 17.15 Table 17.15 Table 17.16 Table 17.17 Table 17.18 Table 17.19 Table 17.20 Table 17.21 Table 17.22 Table 17.23 Table 17.24 Table 17.25 Table 17.26 Table 17.27 Appendices Table A.1 Table A.2 Table A.3 Table A.4 Table C.1 Table D.1 Table D.2 Table D.3
LCD Characteristics............................................................................................... Absolute Maximum Ratings .................................................................................. DC Characteristics ................................................................................................. Control Signal Timing............................................................................................ Serial Interface (SCI3) Timing............................................................................... A/D Converter Characteristics ............................................................................... LCD Characteristics............................................................................................... Flash Memory Characteristics................................................................................ Absolute Maximum Ratings .................................................................................. DC Characteristics (1)............................................................................................ DC Characteristics (2)............................................................................................ DC Characteristics (3)............................................................................................ DC Characteristics (4)............................................................................................ DC Characteristics (5)............................................................................................ Control Signal Timing............................................................................................ Serial Interface (SCI3) Timing............................................................................... A/D Converter Characteristics ............................................................................... LCD Characteristics............................................................................................... Flash Memory Characteristics................................................................................ Power Supply Voltage Detection Circuit Characteristics (1)................................. Power Supply Voltage Detection Circuit Characteristics (2)................................. Power Supply Voltage Detection Circuit Characteristics (3)................................. Power Supply Voltage Detection Circuit Characteristics (4)................................. Power Supply Voltage Detection Circuit Characteristics (5)................................. Power-On Reset Circuit Characteristics................................................................. Watchdog Timer Characteristics............................................................................
362 363 368 375 378 379 381 382 384 389 390 391 392 393 398 399 400 401 402 404 404 405 406 407 407 408
Instruction Set ........................................................................................................ Operation Code Map.............................................................................................. Number of States Required for Execution ............................................................. Number of Cycles in Each Instruction ................................................................... Port States .............................................................................................................. Product Code Lineup of H8/3802 Group ............................................................... Product Code Lineup of H8/38004 Group ............................................................. Product Code Lineup of H8/38104 Group .............................................................
415 425 427 427 445 446 447 449
Rev. 6.00 Mar 15, 2005 page l of l
Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8/300L central processing unit Complete instruction set compatibility with H8/300 CPU Sixteen 8-bit general registers (Can be used as eight 16-bit general registers) 55 basic instructions * Various peripheral functions Timer A (can be used as a time base for a clock) Timer F (16-bit timer) Asynchronous event counter (16-bit timer) Watchdog timer (WDT) (H8/38004, H8/38002S Group and H8/38104 Group only) SCI3 (Asynchronous or clocked synchronous serial communication interface) 10-bit PWM 10-bit A/D converter LCD controller/driver Power-on reset and low-voltage detect circuits (H8/38104 Group only)
Rev. 6.00 Mar 15, 2005 page 1 of 502 REJ09B0024-0600
Section 1 Overview
* On-chip memory
Product Classification Flash memory version (F-ZTATTM version*1) H8/38004 H8/38002 H8/38104 H8/38102 PROM version (ZTATTM version*2) Mask ROM version H8/3802 H8/3802 H8/3801 H8/3800 H8/38004 H8/38003 H8/38002 H8/38001 H8/38000 H8/38002S H8/38001S H8/38000S H8/38104 H8/38103 H8/38102 H8/38101 H8/38100 Model HD64F38004 HD64F38002 HD64F38104 HD64F38102 HD6473802 HD6433802 HD6433801 HD6433800 HD64338004 HD64338003 HD64338002 HD64338001 HD64338000 HD64338002S HD64338001S HD64338000S HD64338104 HD64338103 HD64338102 HD64338101 HD64338100 ROM 32 kbytes 16 kbytes 32 kbytes 16 kbytes 16 kbytes 16 kbytes 12 kbytes 8 kbytes 32 kbytes 24 kbytes 16 kbytes 12 kbytes 8 kbytes 16 kbytes 12 kbytes 8 kbytes 32 kbytes 24 kbytes 16 kbytes 12 kbytes 8 kbytes RAM 1 kbyte 1 kbyte 1 kbyte 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes
Notes: 1. F-ZTAT is a trademark of Renesas Technology Corp. 2. ZTAT is a trademark of Renesas Technology Corp.
* General I/O ports I/O pins: 39 I/O pins Input-only pins: 5 input pins Output-only pins: 6 output pins (5 pins on H8/38104 Group) * Supports various power-down modes
Rev. 6.00 Mar 15, 2005 page 2 of 502 REJ09B0024-0600
Section 1 Overview
* Compact package
Package QFP-64 LQFP-64 LQFP-64 DP-64S Die Code FP-64A FP-64E FP-64K* DP-64S Body Size 14.0 x 14.0 mm 10.0 x 10.0 mm 10.0 x 10.0 mm Pin Pitch 0.8 mm 0.5 mm 0.5 mm 1.0 mm
17.0 x 57.6 mm
The DP-64S package is only for the H8/3802 Group. The chip is not supported by the H8/38104 Group. Note: * Under development. The package dimensions of the FP-64K and FP-64E differ. For details, see appendix E, Package Dimensions.
Rev. 6.00 Mar 15, 2005 page 3 of 502 REJ09B0024-0600
Section 1 Overview
1.2
Internal Block Diagram
Vss Vss = AVss Vcc RES TEST PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC
x1 x2
Subclock oscillator
H8/300L CPU
OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16
System clock oscillator
RAM
Port 3
Asynchronous event counter (AEC)
Port 4
Port 8
Timer A
Port 9
ROM
Port A
P95 P94 P93 P92 P91/PWM2 P90/PWM1
P80/SEG25
Port 5
10-bit PWM1 Timer F 10-bit PWM2
LCD power supply
P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0
Port 6
RAM
AVcc
10-bit A/D converter
Large-current (25 mA/pin) high-voltage open-drain pin (7 V) Large-current (10 mA/pin) high-voltage open-drain pin (7 V) High-voltage (7 V) input pin
Figure 1.1 Internal Block Diagram of H8/3802 Group
Rev. 6.00 Mar 15, 2005 page 4 of 502 REJ09B0024-0600
Port B
LCD controller/driver
Port 7
Section 1 Overview
Vss Vss = AVss Vcc RES TEST PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC
x1 x2
Subclock oscillator
H8/300L CPU
OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16
System clock oscillator
RAM
Port 3
ROM
Asynchronous event counter (AEC) Timer A
Port A
Port 4
P95 P94 P93 P92 P91/PWM2 P90/PWM1
Port 8
Port 9
P80/SEG25
Port 5
10-bit PWM1 Timer F 10-bit PWM2
P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0
WDT
Port 6
SCI3
LCD controller/driver
AVcc
10-bit A/D converter
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator.
Figure 1.2 Internal Block Diagram of H8/38004 Group
Rev. 6.00 Mar 15, 2005 page 5 of 502 REJ09B0024-0600
Port B
LCD power supply
Port 7
Section 1 Overview
CVcc Vss Vss = AVss Vcc RES TEST PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC
x1 x2
Subclock oscillator
H8/300L CPU
OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16
System clock oscillator
RAM
Port 3
ROM
Port 4
Port 8
Timer A
Power-on reset and low-voltage detection circuit
Port 9
Asynchronous event counter (AEC)
Port A
P95 P93/Vref P92 P91/PWM2 P90/PWM1
P80/SEG25
Port 5
10-bit PWM1 Timer F 10-bit PWM2
P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1/extU PB0/AN0/extD
WDT
Port 6
SCI3
LCD controller/driver
AVcc
10-bit A/D converter
: Large current (15 mA) pin Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator.
Figure 1.3 Internal Block Diagram of H8/38104 Group
Rev. 6.00 Mar 15, 2005 page 6 of 502 REJ09B0024-0600
Port B
LCD power supply
Port 7
Section 1 Overview
1.3
Pin Arrangement
P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14 35
P66/SEG15 34
48
47
46
45
44
43
42
41
40
39
38
37
36
33
P67/SEG16
P60/SEG9
P90/PWM1 P91/PWM2 P92 P93 P94 P95 Vss IRQAEC P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVcc PB0/AN0 PB1/AN1 PB2/AN2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
10 11 12 13 14 15 1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
P70/SEG17 P71/SEG18 P72/SEG19 P73/SEG20 P74/SEG21 P75/SEG22 P76/SEG23 P77/SEG24 P80/SEG25 PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 V3 V2 V1
FP-64A, FP-64E, FP-64K (Top view)
OSC2
OSC1
PB3/IRQ1/AN3
TEST
RES
X1
X2
P32/TMOFH
P33
P34
P35
P36/AEVH
Vss=AVss
P31/TMOFL
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator.
Figure 1.4 Pin Arrangement of H8/3802, H8/38004 and H8/38002S Group (FP-64A, FP-64E, FP-64K)
Rev. 6.00 Mar 15, 2005 page 7 of 502 REJ09B0024-0600
P37/AEVL
Vcc
Section 1 Overview
P40/SCK32 P41/RXD32 P42/TXD32 P43/ AVcc PB0/AN0 PB1/AN1 PB2/AN2 PB3/ /AN3 X1 X2 VSS=AVSS OSC2 OSC1 TEST P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL Vcc V1 V2 V3 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P80/SEG25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
IRQAEC Vss P95 P94 P93 P92 P91/PWM2 P90/PWM1 P50/ P51/ P52/ P53/ P54/ P55/ P56/ P57/ P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 P70/SEG17 P71/SEG18 P72/SEG19 P73/SEG20 P74/SEG21 P75/SEG22 P76/SEG23 P77/SEG24 /SEG1 /SEG2 /SEG3 /SEG4 /SEG5 /SEG6 /SEG7 /SEG8
DP-64S (Top view)
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Figure 1.5 Pin Arrangement of H8/3802 Group (DP-64S)
Rev. 6.00 Mar 15, 2005 page 8 of 502 REJ09B0024-0600
Section 1 Overview
P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14 35
P66/SEG15 34
48
47
46
45
44
43
42
41
40
39
38
37
36
33
P67/SEG16
P60/SEG9
P90/PWM1 P91/PWM2 P92 P93/Vref CVcc P95 Vss IRQAEC P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVcc PB0/AN0/extD PB1/AN1/extU PB2/AN2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
10 11 12 13 14 15 1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
P70/SEG17 P71/SEG18 P72/SEG19 P73/SEG20 P74/SEG21 P75/SEG22 P76/SEG23 P77/SEG24 P80/SEG25 PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 V3 V2 V1
FP-64A, FP-64E (Top view)
OSC2
OSC1
PB3/IRQ1/AN3
TEST
RES
X1
X2
P32/TMOFH
P33
P34
P35
P36/AEVH
Vss=AVss
P31/TMOFL
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator.
Figure 1.6 Pin Arrangement of H8/38104 Group (FP-64A, FP-64E)
Rev. 6.00 Mar 15, 2005 page 9 of 502 REJ09B0024-0600
P37/AEVL
Vcc
Section 1 Overview
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
1
Model name
49 48 47 46
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (0, 0) X Y
45 44 43 42 41 40 39 38 37 36 35
17 34
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Chip size: 3.60 mm x 3.73 mm Voltage level on the back of the chip: GND
Figure 1.7 Pad Arrangement of HCD6433802, HCD6433801, and HCD6433800 (Top View)
Rev. 6.00 Mar 15, 2005 page 10 of 502 REJ09B0024-0600
33
Section 1 Overview
Table 1.1
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Pad Coordinate of HCD6433802, HCD6433801, and HCD6433800
Coordinate Pad No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Coordinate Pad Name P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 P54/WKP4/SEG5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 P90/PWM1 P91/PWM2 P92 P93 P94 P95 Vss IRQAEC P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVcc X (m) 1400 1578 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1677 1578 1411 1193 1051 850 650 400 200 -298 -435 -572 -752 -1036 Y (m) -1742 -1742 -1401 -1190 -950 -801 -608 -459 -310 -160 -11 121 252 383 801 950 1190 1402 1742 1742 1742 1742 1742 1742 1742 1742 1742 1742 1742 1742 1742
Pad Name PB3/IRQ1/AN3 X1 X2 AVss Vss OSC2 OSC1 TEST
SER
X (m) -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1677 -1578 -1339 -1193 -1049 -850 -400 -200 0 320 451 583 850 1051 1193
Y (m) 1495 1084 943 765 619 488 356 225 94 -40 -176 -313 -450 -587 -943 -1083 -1404 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742 -1742
P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL Vcc V1 V2 V3 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19
Rev. 6.00 Mar 15, 2005 page 11 of 502 REJ09B0024-0600
Section 1 Overview Pad No. 63 64 Coordinate Pad Name PB0/AN0 PB1/AN1 X (m) -1170 -1400 Y (m) 1742 1742 Pad No. 65 Coordinate Pad Name PB2/AN2 X (m) -1578 Y (m) 1742
Note: The power supply (Vss) pads in pad numbers 4, 5, and 56 must not be open but connected. The TEST pad in pad number 8 must be connected to the Vss voltage level. If not, this LSI does not operate correctly. The coordinate values indicate center positions of pads and the accuracy is 5 m. The home-point position is center of the chip and the center is located at half the distance between the upper and lower pads and left and right pads.
Rev. 6.00 Mar 15, 2005 page 12 of 502 REJ09B0024-0600
Section 1 Overview
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48 47
2
46
3
45
4
44 43 Y
5
6 7 8 9 10 11 12 13 14 (0, 0) X
42 41 40 39
38
37 36
15
35 16 34 33
Model name
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Chip size: 2.73 mm x 3.27 mm Voltage level on the back of the chip: GND : NC pad
Figure 1.8 Pad Arrangement of HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000 (Top View)
Rev. 6.00 Mar 15, 2005 page 13 of 502 REJ09B0024-0600
32
Section 1 Overview
Table 1.2
Pad Coordinate of HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000
Coordinate X (m) -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -1224 -922 -799 -676 -553 -430 -307 -185 -62 53 176 299 421 544 Y (m) 1214 957 786 596 406 234 120 6 -108 -222 -336 -450 -564 -678 -849 -1142 -1484 -1484 -1484 -1484 -1484 -1484 -1484 -1484 -1484 -1484 -1484 -1484 -1484 Pad No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Coordinate Pad Name P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 P54/WKP4/SEG5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 P90/PWM1 P91/PWM2 P92 P93 P94 P95 Vss IRQAEC P40/SCK32 P41/RXD32 X (m) 667 790 913 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 1215 913 790 667 544 421 299 176 37 -77 -200 Y (m) -1484 -1484 -1484 -1194 -1080 -909 -738 -566 -395 -224 -52 119 233 404 576 747 919 1090 1206 1494 1494 1494 1494 1494 1494 1494 1494 1494 1494
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pad Name PB3/IRQ1/AN3 X1 X2 Vss = AVss OSC2 OSC1 TEST
SER
P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL Vcc V1 V2 V3 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20
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Section 1 Overview Pad No. 59 60 61 Coordinate Pad Name P42/TXD32 P43/IRQ0 AVcc X (m) -323 -446 -569 Y (m) 1494 1494 1494 Pad No. 62 63 64 Coordinate Pad Name PB0/AN0 PB1/AN1 PB2/AN2 X (m) -692 -815 -937 Y (m) 1494 1494 1494
Note: The power supply (Vss) pads in pad numbers 4 and 55 must not be open but connected. The TEST pad in pad number 7 must be connected to the Vss voltage level. If not, this LSI does not operate correctly. The coordinate values indicate center positions of pads and the accuracy is 5 m. The home-point position is center of the chip and the center is located at half the distance between the upper and lower pads and left and right pads.
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Section 1 Overview
65 64 63 62 61 60 59 58 57 55 54 53 52 51 50 56
Model name 1 49 48 2 47 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (0, 0) X 46 45 Y 44 43 42 41 40 39 38 37 36 35 34
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Product Model Name Model Name on Chip HCD64F38004 HCD64F38004C4 HCD64F38002 HCD64F38002C4 HD64F38004 HD64F38004-4 HD64F38004 HD64F38004-4
Chip size: 4.09 mm x 3.82 mm Voltage level on the back of the chip: GND : NC pad
Figure 1.9 Pad Arrangement of HCD64F38004 and HCD64F38002 (Top View)
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33
Section 1 Overview
Table 1.3
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Pad Coordinate of HCD64F38004 and HCD64F38002
Coordinate Pad No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Coordinate Pad Name P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 P54/WKP4/SEG5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 P90/PWM1 P91/PWM2 P92 P93 P94 P95 Vss IRQAEC P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVcc X (m) 1411 1628 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1914 1628 1368 1113 976 759 542 324 96 -109 -327 -545 -762 -980 Y (m) -1779 -1779 -1496 -1297 -1098 -899 -700 -500 -302 -103 96 295 495 694 893 1092 1291 1490 1779 1779 1779 1779 1779 1779 1779 1779 1779 1779 1779 1779 1779
Pad Name PB3/IRQ1/AN3 X1 X2 Vss Vss = AVss OSC2 OSC1 TEST
SER
X (m) -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1915 -1623 -1406 -1189 -973 -756 -539 -323 -106 111 328 544 761 978 1194
Y (m) 1490 1182 1022 926 786 648 495 295 96 -103 -302 -486 -657 -750 -989 -1247 -1438 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779 -1779
P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL Vcc V1 V2 V3 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19
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Section 1 Overview Pad No. 63 64 Coordinate Pad Name PB0/AN0 PB1/AN1 X (m) -1198 -1414 Y (m) 1779 1779 Pad No. 65 Coordinate Pad Name PB2/AN2 X (m) -1613 Y (m) 1779
Note: The power supply (Vss) pads in pad numbers 4, 5, and 56 must not be open but connected. The TEST pad in pad number 8 must be connected to the Vss voltage level. If not, this LSI does not operate correctly. The coordinate values indicate center positions of pads and the accuracy is 5 m. The home-point position is center of the chip and the center is located at half the distance between the upper and lower pads and left and right pads.
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Section 1 Overview
1.4
Pin Functions
Pin Functions
Pin No. FP-64A, FP-64E, FP-64K 16
Table 1.4
Type Power source pins
Symbol VCC VSS
DP-64S 24
Pad Pad No.*1*3 No.*2 17 16 4 55 61
I/O Input Input
Functions Power supply pin. Connect this pin to the system power supply. Ground pin. Connect this pin to the system power supply (0V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Power supply pin for the LCD controller/driver. This is the internal step-down power supply pin. To ensure stability, a capacitor with a rating of about 0.1 F should be connected between this pin and the VSS pin. These pins connect to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection.
4 (= AVSS) 12 (= AVSS) 4 55 63 5 56 61 5 62
AVCC
Input
AVSS
4 (= VSS)
12 (= VSS)
4 5 18 19 20 --
4
Input
V1 V2 V3 CVCC*4
17 18 19 53
25 26 27 --
17 18 19 --
Input
Input
Clock pins
OSC1 OSC2
6 5
14 13
7 6
6 5
Input Output
X1 X2
2 3
10 11
2 3
2 3
Input Output
These pins connect to a 32.7685 or 38.4-kHz* crystal resonator for subclocks. See section 4, Clock Pulse Generators, for a typical connection.
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Section 1 Overview
Pin No. FP-64A, FP-64E, FP-64K 8 7 60 1 56
Type System control
Symbol
DP-64S 16 15 4 9 64
Pad Pad 13 2 No.* * No.* 9 8 61 1 57 8 7 60 1 56
I/O Input Input Input
Functions Reset pin. When this driven low, the chip is reset. Test pin. Connect this pin to Vss. Users cannot use this pin. External interrupt request input pins. Can select the rising or falling edge. Asynchronous event counter interrupt input pin. Enables asynchronous event input. On the H8/38104 Group, this must be fixed at VCC or GND because the oscillator is selected by the input level during resets. Refer to section 4, Clock Pulse Generators, for information on the selection method.
TEST Interrupt pins
Timer
AEVL AEVH TMOFL
10-bit PWM PWM1 PWM2
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0PKW 7PKW
1QRI 0QRI
SER
IRQAEC to TMOFH
Input
41 to 48
49 to 56
42 to 49 41 to 48 Input
Wakeup interrupt request input pins. Can select the rising or falling edge. This is an event input pin for input to the asynchronous event counter. This is an output pin for waveforms generated by the timer FL output compare function. This is an output pin for waveforms generated by the timer FH output compare function. These are output pins for waveforms generated by the channel 1 and 2 10-bit PWMs.
15 14 9
23 22 17
16 15 10
15 14 9
Input
Output
10
18
11
10
Output
49 50
57 58
50 51
49 50
Output
Section 1 Overview
Pin No. FP-64A, FP-64E, FP-64K 15 to 9
Type I/O ports
Symbol P37 to P31
DP-64S 23 to 17
Pad Pad 13 2 No.* * No.* 16 to 10 15 to 9
I/O I/O
Functions 7-bit I/O port. Input or output can be designated for each bit by means of the port control register 3 (PCR3). When the onchip emulator is used, pins P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator. 1-bit input port. 3-bit I/O port. Input or output can be designated for each bit by means of the port control register 4 (PCR4). 8-bit I/O port. Input or output can be designated for each bit by means of the port control register 5 (PCR5). 8-bit I/O port. Input or output can be designated for each bit by means of the port control register 6 (PCR6). 8-bit I/O port. Input or output can be designated for each bit by means of the port control register 7 (PCR7). 1-bit I/O port. Input or output can be designated for each bit by means of the port control register 8 (PCR8).
P43 P42 to P40
60 59 to 57
4 3 to 1
61
60
Input
60 to 58 59 to 57 I/O
P57 to P50
41 to 48
49 to 56
42 to 49 41 to 48 I/O
P67 to P60
33 to 40
41 to 48
34 to 41 33 to 40 I/O
P77 to P70
25 to 32
33 to 40
26 to 33 25 to 32 I/O
P80
24
32
25
24
I/O
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Section 1 Overview
Pin No. FP-64A, FP-64E, FP-64K 54 to 49
Type I/O ports
Symbol P95 to P90
DP-64S 62 to 57
Pad Pad 13 2 No.* * No.*
I/O
Functions 6-bit output port. When the onchip emulator is used, pin P95 is unavailable to the user because it is used exclusively by the onchip emulator. In the F-ZTAT version, pin P95 should not be open but pulled up to go high in user mode. Note that the H8/38104 Group is not equipped with a pin 94.
55 to 50 54 to 49 Output
PA3 to PA0
20 to 23
28 to 31
21 to 24 20 to 23 I/O
4-bit I/O port. Input or output can be designated for each bit by means of the port control register A (PCRA). 4-bit input port. Receive data input pin. Transmit data output pin. Clock I/O pin. Analog data input pins. LCD common output pins. LCD segment output pins. Reference voltage input pin. Power supply drop detection voltage input pin. Power supply rise detection voltage input pin.
PB3 to PB0 Serial communication interface (SCI) A/D converter LCD controller/ driver RXD32 TXD32 SCK32 AN3 to AN0
1, 64 to 62 58 59 57 1, 64 to 62
9 to 6 2 3 1 9 to 6 28 to 31 32 to 56 -- -- --
1, 1, Input 65 to 63 64 to 62 59 60 58 58 59 57 Input Output I/O
1, 1, Input 65 to 63 64 to 62 21 to 24 20 to 23 Output 25 to 49 24 to 48 Output -- -- -- -- -- -- Input Input Input
COM4 to 20 to 23 COM1 SEG25 to 24 to 48 SEG1 52 62 63
Low-voltage Vref detection extD circuit 4 (LVD) * extU
Notes: 1. Pad number for HCD6433802, HCD6433801, and HCD6433800 2. Pad number for HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000 3. Pad number for HCD64F38004 and HCD64F38002 4. H8/38104 Group only 5. Does not apply to H8/38104 Group Rev. 6.00 Mar 15, 2005 page 22 of 502 REJ09B0024-0600
Section 2 CPU
Section 2 CPU
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation.
2.1
Features
* General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit registers * Fifty-five basic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@Rn] Register indirect with displacement [@(d:16,Rn)] Register indirect with post-increment or pre-decrement [@Rn+ or @-Rn] Absolute address [@aa:8 or @aa:16] Immediate [#xx:8 or #xx:16] Program-counter relative [@(d:8,PC)] Memory indirect [@@aa:8] * 64-kbyte address space * High-speed operation All frequently-used instructions execute in two to four states 8/16-bit register-register add/subtract : 0.25 s* 8 x 8-bit multiply : 1.75 s* 16 / 8-bit divide : 1.75 s* Note: * These values are at = 8 MHz. * Power-down state Transition to power-down state by SLEEP instruction
CPU30L0A_000020020900
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Section 2 CPU
2.2
Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.
(PROM and Mask ROM versions) H'0000 Interrupt vector area H'0029 H'002A
On-chip ROM (16 kbytes)
H'3FFF
Not used
H'F740 LCD RAM (13 bytes) H'F74C Not used H'FB80 On-chip RAM (1 kbyte) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF
Figure 2.1(1) H8/3802 Memory Map
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Section 2 CPU
(Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A
On-chip ROM (12 kbytes)
H'2FFF
Not used
H'F740 H'F74C
LCD RAM (13 bytes)
Not used H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF
Figure 2.1(2) H8/3801 Memory Map
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Section 2 CPU
(Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A
On-chip ROM (8 kbytes)
H'1FFF Not used
H'F740 H'F74C
LCD RAM (13 bytes) Not used
H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF
Figure 2.1(3) H8/3800 Memory Map
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Section 2 CPU
(Flash memory version) H'0000 Interrupt vector area H'0029 H'002A H'0029 H'002A H'0000 Interrupt vector area (Mask ROM version)
On-chip ROM (32 kbytes) On-chip ROM (32 kbytes) H'7000 Firmware for on-chip emulator*1 H'7FFF Not used H'F020 H'F02B Internal I/O register Not used H'F740 LCD RAM (13 bytes) H'F74C H'F780 H'FB7F H'FB80 H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF H'FFFF Not used Work area for flash memory reprogramming*2 (1 kbyte) On-chip RAM (2 kbytes) User area (1 kbyte) H'F74C Not used H'F740 LCD RAM (13 bytes) Not used H'7FFF
H'FB80 H'FF7F H'FF80
On-chip RAM (1 kbyte) Internal I/O register (128 bytes)
Note: 1. When the on-chip emulator is used, this area is unavailable to the user. 2. When flash memory is programmed, this area is used by the programming control program. When the on-chip emulator is used, this area is unavailable to the user.
Figure 2.1(4) H8/38004, H8/38104 Memory Map
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Section 2 CPU
(Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A
On-chip ROM (24 kbytes)
H'5FFF
Not used
H'F740 LCD RAM (13 bytes) H'F74C Not used H'FB80 On-chip RAM (1 kbyte) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF
Figure 2.1(5) H8/38003, H8/38103 Memory Map
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Section 2 CPU
(Flash memory version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (16 kbytes) H'3FFF Not used H'7000 Firmware for on-chip emulator*1 H'7FFF Not used H'F020 H'F02B Internal I/O register Not used H'F740 LCD RAM (13 bytes) H'F74C Not used H'F780 H'FB7F H'FB80 H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF H'FFFF Work area for flash memory reprogramming*2 (1 kbyte) On-chip RAM (2 kbytes) User area (1 kbyte) Not used H'F74C H'F740 LCD RAM (13 bytes) Not used H'3FFF H'0029 H'002A On-chip ROM (16 kbytes) H'0000 Interrupt vector area (Mask ROM version)
H'FB80 H'FF7F H'FF80
On-chip RAM (1 kbyte) Internal I/O register (128 bytes)
Notes: 1. This area is unavailable to the user. 2. When flash memory is programmed, this area is used by the programming control program. When the on-chip emulator is used, this area is unavailable to the user.
Figure 2.1(6) H8/38002, H8/38102 Memory Map
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Section 2 CPU
(Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (16 kbytes) H'3FFF
Not used
H'F740 LCD RAM (13 bytes) H'F74C
Not used
H'FD80 H'FF7F H'FF80
On-chip RAM (512 byte) Internal I/O register (128 bytes)
H'FFFF
Figure 2.1(7) H8/38002S Memory Map
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Section 2 CPU
(Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (12 kbytes) H'2FFF
Not used
H'F740 H'F74C
LCD RAM (13 bytes)
Not used
H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 H'FFFF Internal I/O register (128 bytes)
Figure 2.1(8) H8/38001, H8/38001S, H8/38101 Memory Map
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Section 2 CPU
(Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (8 kbytes) H'1FFF
Not used
H'F740 H'F74C
LCD RAM (13 bytes)
Not used
H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 H'FFFF Internal I/O register (128 bytes)
Figure 2.1(9) H8/38000, H8/38000S, H8/38100 Memory Map
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Section 2 CPU
2.3
Register Configuration
Figure 2.2 shows the internal register configuration of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
General registers (Rn)
7 R0H R1H R2H R3H R4H R5H R6H R7H
0
7 R0L R1L R2L R3L R4L R5L R6L
0
(SP)
R7L
Control register (CR)
15 PC 7 CCR I 6 U 5 H 4 U 3 N 2 Z 1 V
0
0 C
Legend: SP: PC: CCR: I: U: H: N: Z: V: C: Stack pointer Program counter Condition code register Interrupt mask bit User bit Half-carry flag Negative flag Zero flag Overflow flag Carry flag
Figure 2.2 CPU Registers
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Section 2 CPU
2.3.1
General Registers
All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the upper bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception handling and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.3, SP (R7) points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.3 Stack Pointer 2.3.2 Program Counter (PC)
This 16-bit counter indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0).
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Section 2 CPU
2.3.3
Condition Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I), half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized.
Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts when set to 1. The I bit is set to 1 at the start of an exception-handling sequence. 6 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
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Section 2 CPU Initial Value
Bit 0
Bit Name C
R/W
Description Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
Undefined R/W
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. For the action of each instruction on the flag bits, refer to H8/300L Series Programming Manual. 2.3.4 Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the initial value of the stack pointer (R7) is undefined. The stack pointer should be initialized by software, by the first instruction executed after a reset.
2.4
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.4.1 General Register Data Formats
Figure 2.4 shows the data formats in general registers.
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Section 2 CPU
Data Type Register No. 7 1-bit data RnH 7 6 5 4 3 2 1 Data Format 0 0 Don't care
7 1-bit data RnL Don't care 7 6 5 4 3 2 1
0 0
7 Byte data RnH MSB
0 LSB Don't care
7 Byte data RnL Don't care MSB
0 LSB
15 Word data Rn MSB
0 LSB
7 4-bit BCD data RnH Upper digit
4
3 Lower digit
0 Don't care
7 4-bit BCD data RnL Don't care Upper digit
4
3 Lower digit
0
Legend: RnH: Upper byte of general register RnL: LSB: Lower byte of general register Least significant bit MSB: Most significant bit
Figure 2.4 General Register Data Formats
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Section 2 CPU
2.4.2
Memory Data Formats
Figure 2.5 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. The same applies to instruction codes.
Data Type Address Data Format
7 1-bit data Address n 7 6 5 4 3 2 1
0 0
Byte data
Address n
MSB
LSB
Even address MSB Word data Odd address
Upper 8 bits Lower 8 bits LSB
Even address MSB Byte data (CCR) on stack Odd address MSB
CCR CCR*
LSB LSB
Even address MSB Word data on stack Odd address LSB
Note: * Ignored on return Legend: CCR: Condition code register
Figure 2.5 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored.
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Section 2 CPU
2.5
Instruction Set
The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2.1. Table 2.1
Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer
Instruction Set
Instructions MOV, PUSH*1, POP*1 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Number 1 14 4 8 14 5 8 1 Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine language. 2. Bcc is the general name for conditional branch instructions.
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below.
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Section 2 CPU
Table 2.2
Symbol Rd Rs Rn
Operation Notation
Description General register (destination) General register (source) General register Destination operand Source operand Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 3-, 8-, or 16-bit length Contents of operand indicated by effective address
(EAd), (EAs), CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16 ( ), < >
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2.5.1
Data Transfer Instructions
Table 2.3 describes the data transfer instructions. Table 2.3
Instruction MOV
Data Transfer Instructions
Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes.
POP PUSH
W W
@SP+ Rn Pops a general register from the stack. Equivalent to MOV.W@SP+, Rn. Rn @-SP Pushes a general register onto the stack. Equivalent to MOV.W Rn, @- SP.
Note:
*
Refers to the operand size. B: Byte W: Word
For details on data access, see section 2.9.1, Notes on Data Access to Empty Areas and section 2.9.2, Access to Internal I/O Registers. Figure 2.6 shows the instruction formats of data transfer instructions.
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Section 2 CPU
15 8 7 0
MOV
Rm Rn
op
15 8 7
rm
rn
0
op
15 8 7
rm
rn
0
@Rm
Rn
op disp
15 8 7
rm
rn
@(d: 16, Rm)
Rn
0
@Rm + Rn
Rn,
op
15 8 7
rm
rn
0
@-Rm
op
15
rn
8 7
abs
0
@aa:8
Rn
op abs
15 8 7
rn
@aa:16
Rn
0
op
15
rn
8 7
IMM
0
#xx:8
Rn
op IMM
15 8 7
rn
#xx:16
Rn
0
POP, PUSH
@SP+ Rn Rn, @-SP
op
1
1
1
rn
Legend: op: disp: abs: IMM: Operation field Displacement Absolute address Immediate data rm, rn: Register field
Figure 2.6 Instruction Formats of Data Transfer Instructions
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Section 2 CPU
2.5.2
Arithmetic Operations Instructions
Table 2.4 describes the arithmetic operations instructions. Table 2.4
Instruction ADD SUB
Arithmetic Operations Instructions
Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or addition or subtraction with carry on immediate data and data in a general register. Rd 1 Rd Increments or decrements a general register by 1. Rd 1 Rd, Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register.
ADDX SUBX
B
INC DEC ADDS SUBS DAA DAS MULXU
B W B
B
DIVXU
B
CMP
B/W
NEG
B
Note:
*
Refers to the operand size. B: Byte W: Word
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Section 2 CPU
2.5.3
Logic Operations Instructions
Table 2.5 describes the logic operations instructions. Table 2.5
Instruction AND
Logic Operations Instructions
Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Obtains the one's complement (logical complement) of general register contents.
OR
B
XOR
B
NOT
B
Note:
*
Refers to the operand size. B: Byte
2.5.4
Shift Instructions
Table 2.6 describes the shift instructions. Table 2.6
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B B B B Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag.
Refers to the operand size. B: Byte
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Section 2 CPU
Figure 2.7 shows the instruction formats of arithmetic, logic, and shift instructions.
15 8 7 0
op
15 8 7
rm
rn
0
ADD, SUB, CMP, ADDX, SUBX (Rm)
op
15 8 7
rn
0
ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT
op
15 8 7
rm
rn
0
MULXU, DIVXU
op
15
rn
8 7
IMM
0
ADD, ADDX, SUBX, CMP (#xx:8)
op
15 8 7
rm
rn
0
AND, OR, XOR (Rm)
op
15
rn
8 7
IMM
0
AND, OR, XOR (#xx:8)
op
rn
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Legend: op: IMM: Operation field Immediate data rm, rn: Register field
Figure 2.7 Instruction Formats of Arithmetic, Logic, and Shift Instructions
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Section 2 CPU
2.5.5
Bit Manipulation Instructions
Table 2.7 describes the bit manipulation instructions. Table 2.7
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
*
Refers to the operand size. B: Byte
For details on the bit manipulation instructions, see section 2.9.4, Bit Manipulation Instructions. Figure 2.8 shows the instruction formats of bit manipulation instructions.
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BSET, BCLR, BNOT, BTST
15 8 7 0
Operand Bit No.
: Register direct (Rn) : Immediate (#xx:3) : Register direct (Rn) : Register direct (Rm)
op
15 8 7
IMM
rn
0
Operand Bit No.
op
15 8 7
rm
rn
0
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 0
0
Operand Bit No.
: Register indirect (@Rn) : Immediate (#xx:3)
op op
15 8 7
rn rm
0 0
0 0
0 0
0 0
0
Operand Bit No.
: Register indirect (@Rn) : Register direct (Rm)
op op
15 8 7
abs IMM 0 0 0 0
0
Operand Bit No.
: Absolute address (@aa:8) : Immediate (#xx:3)
op op rm
abs 0 0 0 0
Operand Bit No.
: Absolute address (@aa:8) : Register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15 8 7 0
Operand Bit No.
: Register direct (Rn) : Immediate (#xx:3)
op
15 8 7
IMM
rn
0
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 0
0
Operand Bit No.
: Register indirect (@Rn) : Immediate (#xx:3)
op op IMM
abs 0 0 0 0
Operand Bit No.
: Absolute address (@aa:8) : Immediate (#xx:3)
BIAND, BIOR, BIXOR, BILD, BIST
15 8 7 0
Operand Bit No.
: Register direct (Rn) : Immediate (#xx:3)
op
15 8 7
IMM
rn
0
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 0
0
Operand Bit No.
: Register indirect (@Rn) : Immediate (#xx:3)
op op Legend: op: abs: IMM: Operation field Absolute address Immediate data rm, rn: Register field IMM
abs 0 0 0 0
Operand Bit No.
: Absolute address (@aa:8) : Immediate (#xx:3)
Figure 2.8 Instruction Formats of Bit Manipulation Instructions
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Section 2 CPU
2.5.6
Branch Instructions
Table 2.8 describes the branch instructions. Table 2.8
Instruction Bcc
Branch Instructions
Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
JMP BSR JSR RTS
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine.
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Section 2 CPU
Figure 2.9 shows the instruction formats of branch instructions.
15 8 7 0
op
15
cc
8 7
disp
0
Bcc
op
15 8 7
rm
0
0
0
0
0
JMP (@Rm)
op abs
15 8 7 0
JMP (@aa:16)
op
15 8 7
abs
0
JMP (@@aa:8)
op
15 8 7
disp
0
BSR
op
15 8 7
rm
0
0
0
0
0
JSR (@Rm)
op abs
15 8 7 0
JSR (@aa:16)
op
15 8 7
abs
0
JSR (@@aa:8)
op Legend: op: Operation field cc: rm: Condition field Register field
RTS
disp: Displacement abs: Absolute address
Figure 2.9 Instruction Formats of Branch Instructions
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Section 2 CPU
2.5.7
System Control Instructions
Table 2.9 describes the system control instructions. Table 2.9
Instruction RTE SLEEP LDC STC ANDC ORC XORC NOP Note: *
System Control Instructions
Size* -- -- B B B B B -- Function Returns from an exception-handling routine. Causes a transition from active mode to power-down mode. See section 5, Power-Down Modes, for details. Rs CCR, #IMM CCR Moves immediate data or general register contents to CCR. CCR Rd Copies CCR to a specified general register. CCR #IMM CCR Logically ANDs CCR with immediate data. CCR #IMM CCR Logically ORs CCR with immediate data. CCR #IMM CCR Logically XORs CCR with immediate data. PC + 2 PC Only increments the program counter.
Refers to the operand size. B: Byte
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Section 2 CPU
Figure 2.10 shows the instruction formats of system control instructions.
15 8 7 0
op
15 8 7 0
RTE, SLEEP, NOP
op
15 8 7
rn
0
LDC, STC (Rn)
ANDC, ORC, XORC, LDC (#xx:8)
op Legend: op: rn: Operation field Register field
IMM
IMM: Immediate data
Figure 2.10 Instruction Formats of System Control Instructions 2.5.8 Block Data Transfer Instructions
Table 2.10 describes the block data transfer instructions. Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV Size -- Function If R4L 0 then repeat until @R5+ @R6+ R4L - 1 R4L R4L = 0 else next; Block data transfer instruction. Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6. After the transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, EEPMOV Instruction, for details.
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Section 2 CPU
Figure 2.11 shows the instruction formats of block data transfer instructions.
15 8 7 0
op op Legend: op: Operation field
Figure 2.11 Instruction Format of Block Data Transfer Instructions
2.6
2.6.1
Addressing Modes and Effective Address
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Table 2.11 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16,Rn) @Rn+ @-Rn @aa:8/@aa:16 #xx:8/#xx:16 @(d:8,PC) @@aa:8
Register Direct--Rn The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands.
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Register Indirect--@Rn The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. Register Indirect with Displacement--@(d:16, Rn) The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register (16 bits) to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. Absolute Address--@aa:8/@aa:16 The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535).
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Immediate--#xx:8/#xx:16 The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. Program-Counter Relative--@(d:8, PC) This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number. Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.1, Exception Sources and Vector Address, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.4.2, Memory Data Formats, for further information.
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2.6.2
Effective Address Calculation
Table 2.12 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand.
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No. 3 7 rm 15 Contents of register indicated by rm (16 bits) 7 rm 15 Contents of register indicated by rm (16 bits) 4 rm disp 3 0 15 0 6 4 3 0 15 0 rn 4 3 0 rm rn 0 3 0
Addressing Mode and Instruction Format
Effective Address Calculation Method
Effective Address (EA)
1
Register direct Rn
15
8
op
Operand is contents of registers indicated by rm/rn
2
Register indirect @Rn
15
0
op
3
Register indirect with displacement @(d:16, Rn) 7 6
0
Table 2.12 Effective Address Calculation
15
op
disp
4 15
Register indirect with post-increment or pre-decrement Register indirect with post-increment @Rn+ 0 15 0 Contents of register indicated by rm (16 bits) 7 rm 6 4 3 0 1 or 2 15 Contents of register indicated by rm (16 bits) 7 rm 6 4 3 0 1 or 2 Incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 0
15
op
Register indirect with pre-decrement @-Rn
15
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op
Section 2 CPU
Section 2 CPU
No. Addressing Mode and Instruction Format 15 87 op abs 0 H'FF
Effective Address Calculation Method
Effective Address (EA) 87 0
5
Absolute address @aa:8
15
@aa:16 0 op abs 15 0
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87 op IMM 0 Operand is 1- or 2-byte immediate data 0 op IMM 15 PC contents 87 op disp 0 Sign extension disp 0 15 0
15
6
Immediate
#xx:8
15
#xx:16
15
7
Program-counter relative@ (d: 8, PC)
15
No.
Addressing Mode and Instruction Format
Effective Address Calculation Method
Effective Address (EA)
8 8 abs 15 H'00 Memory contents (16 bits) abs 15 87 0 7 0
Memory indirect@@aa:8
15
op
0
Legend: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data Absolute address abs:
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Section 2 CPU
Section 2 CPU
2.7
Basic Bus Cycle
CPU operation is synchronized by a system clock () or a subclock (SUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.7.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.12 shows the on-chip memory access cycle.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2.12 On-Chip Memory Access Cycle
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Section 2 CPU
2.7.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. For details on the data bus width and number of access states of each register, refer to section 14.1, Register Addresses (Address Order). Two-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of two-state access to an on-chip peripheral module.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (2-State Access)
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Three-State Access to On-Chip Peripheral Modules: Figure 2.14 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle T1 state or SUB T2 state T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access)
Address
Read data
Write data
Figure 2.14 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.8
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state, there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.15. Figure 2.16 shows the state transitions.
CPU state
Reset state The CPU is initialized Program execution state Active (high-speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock
Active (medium-speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Program halt state A state in which the CPU operation is stopped to conserve power
Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode
Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.15 CPU Operation States
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Power-down modes
Section 2 CPU
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source occurs
Interrupt source occurs
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.16 State Transitions
2.9
2.9.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.9.2 Access to Internal I/O Registers
Internal data transfer to or from on-chip peripheral modules other than the on-chip ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Data which is written to lower part of CPU register is not guaranteed.
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Section 2 CPU
Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. 2.9.3 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). 2.9.4 Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. Bit Manipulation in Two Registers Assigned to Same Address: Example 1: Timer load register and timer counter Figure 2.17 shows an example of a timer in which two timer registers are assigned to the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.
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Section 2 CPU
Read Count clock Timer counter
Reload Write Timer load register
Internal data bus
Figure 2.17 Example of Timer Configuration with Two Registers Allocated to Same Address Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P31, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P31 to high-level output. Prior to executing BSET
P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 1 1
BSET instruction executed BSET #1, @PDR3 The BSET instruction is executed for port 3.
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After executing BSET
P37 Input/output Pin state PCR3 PDR3 Input Low level 0 0 P36 Input High level 0 1 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output High level 1 1 1 1
Description on operation When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P31 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'81, but the value read by the CPU is H'41. Next, the CPU sets bit 1 of the read data to 1, changing the PDR3 data to H'43. Finally, the CPU writes H'43 to PDR3, completing execution of BSET. As a result of the BSET instruction, bit 1 in PDR3 becomes 1, and P31 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To prevent this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. Prior to executing BSET MOV.B MOV.B MOV.B #81, R0L, R0L,
P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1
R0L @RAM0 @PDR3
P36 Input High level 0 0 0
The PDR3 value (H'81) is written to a work area in memory (RAM0) as well as to PDR3.
P35 Output Low level 1 0 0
P34 Output Low level 1 0 0
P33 Output Low level 1 0 0
P32 Output Low level 1 0 0
P31 Output Low level 1 0 0
1 1 1
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Section 2 CPU
BSET instruction executed BSET #1, @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0).
After executing BSET MOV.B MOV.B @RAM0, R0L R0L, @PDR3
P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 P36 Input High level 0 0 0
The work area (RAM0) value is written to PDR3.
P35 Output Low level 1 0 0
P34 Output Low level 1 0 0
P33 Output Low level 1 0 0
P32 Output Low level 1 0 0
P31 Output High level 1 1 1
1 1 1
Bit Manipulation in Register Containing Write-Only Bit Example 3: BCLR instruction executed designating PCR3 P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal input at P36. P35 to P31 are output pins that output low-level signals. An example of setting the P31 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. Prior to executing BCLR
P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 1 1
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Section 2 CPU
BCLR instruction executed BCLR #1, @PCR3 The BCLR instruction is executed for PCR3.
After executing BCLR
P37 Input/output Pin state PCR3 PDR3 Output Low level 1 1 P36 Output High level 1 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Input High level 0 0 1 1
Description on operation When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 1 in the read data to 0, changing the data to H'FD. Finally, H'FD is written to PCR3 and BCLR instruction execution ends. As a result of this operation, bit 1 in PCR3 becomes 0, making P31 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins. To prevent this problem, store a copy of the PCR3 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR3. Prior to executing BCLR MOV.B MOV.B MOV.B #3F, R0L, R0L, R0L @RAM0 @PCR3 The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3.
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Section 2 CPU P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 P36 Input High level 0 0 0 P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 1 1 1
BCLR instruction executed BCLR #1, @RAM0 The BCLR instructions executed for the PCR3 work area (RAM0).
After executing BCLR MOV.B MOV.B @RAM0, R0L R0L, @PCR3
P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 P36 Input High level 0 0 0
The work area (RAM0) value is written to PCR3.
P35 Output Low level 1 0 1
P34 Output Low level 1 0 1
P33 Output Low level 1 0 1
P32 Output Low level 1 0 1
P31 Output High level 0 0 0
1 1 1
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Section 2 CPU
Table 2.13 lists the pairs of registers that share identical addresses. Table 2.14 lists the registers that contain write-only bits. Table 2.13 Registers with Shared Addresses
Register Name Port data register 3* Port data register 4* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register A* Note: * Abbreviation PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDRA Address H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDD
Port data registers have the same addresses as input pins.
Table 2.14 Registers with Write-Only Bits
Register Name Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register A Timer control register F PWM1 control register PWM1 data register U PWM1 data register L PWM2 control register PWM2 data register U PWM2 data register L Abbreviation PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCRA TCRF PWCR1 PWDRU1 PWDRL1 PWCR2 PWDRU2 PWDRL2 Address H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFED H'FFB6 H'FFD0 H'FFD1 H'FFD2 H'FFCD H'FFCE H'FFCF
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is pin. The chip is also reset when the watchdog timer overflows, and cleared by the exception handling starts. Exception handling is the same as exception handling by the pin. * Interrupts External interrupts and internal interrupts are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. The following notes apply to the HD64F38004. * Issue Depending on the circuitry status at power-on, a vector 17 (system reservation) interrupt request may be generated. If bit I in CCR is cleared to 0, this interrupt will be accepted just like any other internal interrupt. This can cause processing exceptions to occur, and program execution will eventually halt since there is no procedure for clearing the interrupt request flag in question. * Countermeasure To prevent the above issue from occurring, it is recommended that the following steps be added to programs written for the product.
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SER
SER
Section 3 Exception Handling
Reset Initialize stack pointer Write H'9E to H'FFC3 Read H'FFC3 Write H'F1 to H'FFC3 Write H'BF to H'FFFA Clear I bit in CCR User program Additional steps
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The following is an example in assembler.
.ORG H'0000 .DATA.W INIT .ORG H'0100 INIT: MOV.W #H'FF80:16,SP MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B ANDC.B #H'9E:8,R0L R0L,@H'FFC3:8 @H'FFC3:8,R0L #H'F1:8,R0L R0L,@H'FFC3:8 #H'BF:8,R0L R0L,@H'FFFA:8 #H'7F:8,CCR
; user program
The following is an example in C.
void powerON_Reset(void) { // ------------------------------------------------------unsigned char dummy; *((volatile unsigned char *)0xffc3)= 0x9e; dummy = *((volatile unsigned char *)0xffc3); *((volatile unsigned char *)0xffc3)= 0xf1; *((volatile unsigned char *)0xfffa)= 0xbf; // ------------------------------------------------------set_imask_ccr(0); // clear I bit // user program }
On the mask ROM version of the product, user programs may be used as is (including the additional steps described above) or without the additional steps.
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority.
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Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address
Exception Sources Reset Reserved for system use IRQ0/Low-voltage detect interrupt* IRQ1 IRQAEC Vector Number 0 1 to 3 4 5 6 7, 8 9 Vector Address H'0000 to H'0001 H'0002 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'0011 H'0012 to H'0013 Priority High
Relative Module pin Watchdog timer
Note: * The low-voltage detection circuit and low-voltage detection interrupt are implemented on the H8/38104 Group only.
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SER

External interrupt pin/Low-voltage detect circuit (LVD)*
Reserved for system use WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Reserved for system use Timer A overflow Asynchronous event counter overflow Reserved for system use Timer FL compare match Timer FL overflow Timer FH compare match Timer FH overflow Reserved for system use Transmit end Transmit data empty Transmit data full Receive error A/D conversion end
External interrupt pin
10 11 12 13 14 15 16, 17 18
H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0023 H'0024 to H'0025
Timer A Asynchronous event counter
Timer F
SCI3
A/D converter CPU
19
H'0026 to H'0027 H'0028 to H'0029 Low
Direct transition by execution of 20 SLEEP instruction
Section 3 Exception Handling
3.2
Register Descriptions
Interrupts are controlled by the following registers. * * * * * * * Interrupt edge select register (IEGR) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt request register 1 (IRR1) Interrupt request register 2 (IRR2) Wakeup interrupt request register (IWPR) Wakeup edge select register (WEGR) Interrupt Edge Select Register (IEGR)
3.2.1
Bit 7 to 5 4 to 2 1 0
Bit Name IEG1 IEG0
Initial Value All 1 0 0
R/W W R/W R/W
Description Reserved These bits are always read as 1. Reserved The write value should always be 0. IRQ1 and IRQ0 Edge Select 1: Rising edge of (n = 1 or 0) 0: Falling edge of pin input is detected pin input is detected
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0QRI
1QRI
IEGR selects the direction of an edge that generates interrupt requests of pins and
and
.
nQRI nQRI
Section 3 Exception Handling
3.2.2
Interrupt Enable Register 1 (IENR1)
IENR1 enables timers and external pin interrupts.
Bit 7 Bit Name IENTA Initial Value 0 R/W R/W Description Timer A interrupt enable Enables or disables timer A overflow interrupt requests. 0: Disables timer A interrupt requests 1: Enables timer A interrupt requests 6 5 IENWP 0 W R/W Reserved The write value should always be 0. Wakeup Interrupt Enable Enables or disables WKP7 to WKP0 interrupt requests. 1: Enables 4, 3 2 IENEC2 0 W R/W Reserved 0: Disables to interrupt requests interrupt requests
The write value should always be 0. IRQAEC Interrupt Enable Enables or disables IRQAEC interrupt requests. 0: Disables IRQAEC interrupt requests 1: Enables IRQAEC interrupt requests 1 0 IEN1 IEN0 0 0 R/W R/W IRQ1 and IRQ0 Interrupt Enable Enables or disables IRQ1 and IRQ0 interrupt requests. 1: Enables 0: Disables interrupt requests interrupt requests
(n = 1, 0)
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0PKW 7PKW 0PKW 7PKW
to
nQRI nQRI
Section 3 Exception Handling
3.2.3
Interrupt Enable Register 2 (IENR2)
IENR2 enables direct transition, A/D converter, and timer interrupts.
Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transition Interrupt enable Enables or disables direct transition interrupt requests. 0: Disables direct transition interrupt requests 1: Enables direct transition interrupt requests 6 IENAD 0 R/W A/D Converter Interrupt enable Enables or disables A/D conversion end interrupt requests. 0: Disables A/D converter interrupt requests 1: Enables A/D converter interrupt requests 5, 4 3 IENTFH 0 W R/W Reserved The write value should always be 0. Timer FH Interrupt Enable Enables or disables timer FH compare match or overflow interrupt requests. 0: Disables timer FH interrupt requests 1: Enables timer FH interrupt requests 2 IENTFL 0 R/W Timer FL Interrupt Enable Enables or disables timer FL compare match or overflow interrupt requests. 0: Disables timer FL interrupt requests 1: Enables timer FL interrupt requests 1 0 IENEC 0 W R/W Reserved The write value should always be 0. Asynchronous Event Counter Interrupt Enable Enables or disables asynchronous event counter interrupt requests. 0: Disables asynchronous event counter interrupt requests 1: Enables asynchronous event counter interrupt requests
For details on SCI3 interrupt control, refer to section 10.3.6, Serial Control Register 3 (SCR3).
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Section 3 Exception Handling
3.2.4
Interrupt Request Register 1 (IRR1)
IRR1 is a status flag register for timer A, IRQAEC, IRQ1, and IRQ0 interrupt requests. The corresponding flag is set to 1 when an interrupt request occurs. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7 Bit Name IRRTA Initial Value 0 R/W R/W * Description Timer A Interrupt Request Flag [Setting condition] When the timer A counter value overflows [Clearing condition] When IRRTA = 1, it is cleared by writing 0 6, 4, 3 5 2 IRREC2 1 0 W R/W * Reserved The write value should always be 0. Reserved This bit is always read as 1 and cannot be modified. IRQAEC Interrupt Request Flag [Setting condition] When pin IRQAEC is designated for interrupt input and the designated signal edge is detected [Clearing condition] When IRREC2 = 1, it is cleared by writing 0 1 0 IRRl1 IRRl0 0 0 R/W * R/W * IRQ1 and IRQ0 Interrupt Request Flag [Setting condition] When pin is designated for interrupt input and the designated signal edge is detected (n = 1, 0) [Clearing condition] When IRRI1 and IRRI0 = 1, they are cleared by writing 0 Note: * Only 0 can be written for flag clearing.
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nQRI
Section 3 Exception Handling
3.2.5
Interrupt Request Register 2 (IRR2)
IRR2 is a status flag register for direct transition, A/D converter, timer FH, timer FL, and asynchronous event counter interrupt requests. The corresponding flag is set to 1 when an interrupt request occurs. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W * Description Direct Transition Interrupt Request Flag [Setting condition] When a direct transition is made by executing a SLEEP instruction while the DTON bit = 1 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 6 IRRAD 0 R/W * A/D Converter Interrupt Request Flag [Setting condition] When A/D conversion is completed and the ADSF bit is cleared to 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 5, 4 3 IRRTFH 0 W R/W * Reserved The write value should always be 0. Timer FH Interrupt Request Flag [Setting condition] When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode [Clearing condition] When IRRTFH = 1, it is cleared by writing 0 2 IRRTFL 0 R/W * Timer FL Interrupt Request Flag [Setting condition] When TCFL and OCRFL match in 8-bit timer mode [Clearing condition] When IRRTFL = 1, it is cleared by writing 0 1 W Reserved The write value should always be 0. Rev. 6.00 Mar 15, 2005 page 81 of 502 REJ09B0024-0600
Section 3 Exception Handling Initial Value 0
Bit 0
Bit Name IRREC
R/W R/W *
Description Asynchronous Event Counter Interrupt Request Flag [Setting condition] When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit counter mode [Clearing condition] When IRREC = 1, it is cleared by writing 0
Note:
*
Only 0 can be written for flag clearing.
3.2.6
Wakeup Interrupt Request Register (IWPR)
IWPR is a status flag register for to interrupt requests. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7 6 5 4 3 2 1 0 Note: * Bit Name IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *
Only 0 can be written for flag clearing.
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0PKW 7PKW
Description Wakeup Interrupt Request Flag 7 to 0 [Setting condition] When pin WKPn is designated for wakeup input and the designated edge is detected (n = 7 to 0) [Clearing condition] When IWPFn= 1, it is cleared by writing 0
Section 3 Exception Handling
3.2.7
Wakeup Edge Select Register (WEGR) .
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Bit Name WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Edge Select 7 to 0 pin input sensing. pin falling edge is detected pin rising edge is detected
0: 1:
(n = 7 to 0)
3.3
Reset Exception Handling
When the pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure pin low until the clock pulse generator output that this LSI is reset at power-on, hold the stabilizes. To reset the chip during operation, hold the pin low for at least 10 system clock cycles. When the pin goes high after being held low for the necessary time, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset exception handling sequence is as follows. However, refer to section 14.3.1, Power-On Reset Circuit, for information on the reset sequence for the H8/38104 Group, which has a built-in power-on reset function. 1. Set the I bit in the condition code register (CCR) to 1. 2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address.
SER
nPKW nPKW nPKW
Selects
nPKW
WEGR specifies rising or falling edge sensing for pins
nPKW
SER
SER
SER
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Section 3 Exception Handling
3.4
3.4.1
Interrupt Exception Handling
External Interrupts
There are external interrupts, WKP7 to WKP0, IRQ1, IRQ0, and IRQAEC. WKP7 to WKP0 Interrupts to . These WKP7 to WKP0 interrupts are requested by input signals to pins interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WKEGS7 to WKEGS0 in WEGR. to are designated for interrupt input in PMR5 and the designated signal When pins edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1. IRQ1 and IRQ0 Interrupts and . These interrupts IRQ1 and IRQ0 interrupts are requested by input signals to pins are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG1 and IEG0 in IEGR. When pins and are designated for interrupt input by PMRB and PMR2 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bits IEN1 and IEN0 in IENR1.
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0PKW 7PKW 0QRI
1QRI
0PKW 7PKW 0QRI 1QRI
Section 3 Exception Handling
IRQAEC Interrupt The IRQAEC interrupt is requested by an input signal to pin IRQAEC. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR. When bit IENEC2 in IENR1 is designated for interrupt input and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
Reset cleared Initial program instruction prefetch Vector fetch Internal processing
Internal address bus Internal read signal Internal write signal Internal data bus (16 bits)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction
Figure 3.1 Reset Sequence 3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For direct transition interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IRR2. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
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Section 3 Exception Handling
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. Interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. Then, the I bit in CCR is set to 1, masking further interrupts. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling. 6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC. Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. Notes: 1. When disabling interrupts by clearing bits in the interrupt enable register, or when clearing bits in the interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area
SP (R7) SP + 1 SP + 2 SP + 3 SP + 4
CCR CCR* PCH PCL Even address
Prior to start of interrupt exception handling
PC and CCR saved to stack
After completion of interrupt exception handling
Legend: PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. Register contents must always be saved and restored by word length, starting from an even-numbered address. * Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling 3.4.4 Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2
Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Not including EEPMOV instruction.
Interrupt Wait States
States 1 to 13 4 2 4 4 Total 15 to 27
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Interrupt is accepted
Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing Stack access Vector fetch
Prefetch instruction of Internal interrupt-handling routine processing
Section 3 Exception Handling
Interrupt request signal
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(1) (3) (5) (6) (8) (9) (2) (4) (1) (7) (9) (10)
Internal address bus
Internal read signal
Internal write signal
Figure 3.3 Interrupt Sequence
Internal data bus (16 bits)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine
Section 3 Exception Handling
3.5
3.5.1
Usage Notes
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.W #xx: 16, SP). 3.5.2 Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. 3.5.3 Interrupt Request Flag Clearing Method
Use the following recommended method for flag clearing in the interrupt request registers (IRR1, IRR2, and IWPR). Recommended Method: Perform flag clearing with only one instruction. Either a bit manipulation instruction or a data transfer instruction in bytes can be used. Two examples of coding for clearing IRRI1 (bit 1 in IRR1) are shown below: * BCR #1,@IRR1:8 * MOV.B R1L,@IRR1:8 (Set B11111101 to R1L in advance) Malfunction Example: When flag clearing is performed with several instructions, a flag, other than the intended one, which was set while executing one of those instructions may be accidentally cleared, and thus cause incorrect operations to occur. An example of coding for clearing IRRI1 (bit 1 in IRR1), in which IRRI0 is also cleared and the interrupt becomes invalid is shown below. MOV.B @IRR1:8,R1L AND.B #B11111101,R1L MOV.B R1L,@IRR1:8 At this point, IRRI0 is 0. IRRI0 becomes 1 here. IRRI0 is cleared to 0.
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Section 3 Exception Handling
In the above example, an IRQ0 interrupt occurs while the AND.B instruction is executed. Since not only the original target IRRI1, but also IRRI0 is cleared to 0, the IRQ0 interrupt becomes invalid. 3.5.4 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQAEC, , , and to , the interrupt request flag may be set to 1. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. Table 3.3 lists the interrupt request flags which are set to 1 and the conditions. Table 3.3 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request Flags Set to 1 Conditions IRR1 IRREC2 IRRI1 When the edge designated by AIEGS1 and AIEGS0 in AEGSR is input while IENEC2 in IENRI is set to 1.
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0QRI
When IRQ0 bit in PMR2 is changed from 1 to 0 while pin and IEG0 bit in IEGR = 1.
0QRI
IRRI0
When IRQ0 bit in PMR2 is changed from 0 to 1 while pin and IEG0 bit in IEGR = 0.
1QRI
When IRQ1 bit in PMRB is changed from 1 to 0 while pin and IEG1 bit in IEGR = 1.
1QRI
0PKW 7PKW
0QRI 1QRI
When IRQ1 bit in PMRB is changed from 0 to 1 while pin and IEG1 bit in IEGR = 0.
is low is low is low is low
Section 3 Exception Handling Interrupt Request Flags Set to 1 Conditions
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0PKW
When PMR5 bit WKP0 is changed from 1 to 0 while pin and WEGR bit WKEGS0 = 1.
0PKW
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin and WEGR bit WKEGS0 = 0.
1PKW
When PMR5 bit WKP1 is changed from 1 to 0 while pin and WEGR bit WKEGS1 = 1.
1PKW
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin and WEGR bit WKEGS1 = 0.
2PKW
When PMR5 bit WKP2 is changed from 1 to 0 while pin and WEGR bit WKEGS2 = 1.
2PKW
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin and WEGR bit WKEGS2 = 0.
3PKW
When PMR5 bit WKP3 is changed from 1 to 0 while pin and WEGR bit WKEGS3 = 1.
3PKW
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin and WEGR bit WKEGS3 = 0.
4PKW
When PMR5 bit WKP4 is changed from 1 to 0 while pin and WEGR bit WKEGS4 = 1.
4PKW
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin and WEGR bit WKEGS4 = 0.
5PKW
When PMR5 bit WKP5 is changed from 1 to 0 while pin and WEGR bit WKEGS5 = 1.
5PKW
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin and WEGR bit WKEGS5 = 0.
6PKW
When PMR5 bit WKP6 is changed from 1 to 0 while pin and WEGR bit WKEGS6 = 1.
6PKW
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin and WEGR bit WKEGS6 = 0.
7PKW
When PMR5 bit WKP7 is changed from 1 to 0 while pin and WEGR bit WKEGS7 = 1.
7PKW
IWPR
IWPF7
When PMR5 bit WKP7 is changed from 0 to 1 while pin and WEGR bit WKEGS7 = 0.
is low is low is low is low is low is low is low is low is low is low is low is low is low is low is low is low
Section 3 Exception Handling
Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.)
CCR I bit 1
Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0
CCR I bit 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1 Features
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. In the H8/38104 Group, the system clock pulse generator includes an on-chip oscillator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator and a subclock divider. Figure 4.1 shows a block diagram of the clock pulse generators of the H8/3802, H8/38004 and H8/38002S Group. Figure 4.2 shows a block diagram of the clock pulse generators of the H8/38104 Group.
OSC/2 OSC1 OSC2 System clock oscillator OSC (fOSC) System clock divider (1/2) OSC/16 OSC/32 OSC/64 OSC/128 Prescaler S (13 bits) /2 to /8192 W X1 X2 Subclock oscillator W/2 W (fW) Subclock divider (1/2, 1/4, 1/8) W/4 W/8 SUB W/2 W/4 Prescaler W (5 bits) W/8 to W/128
System clock divider
System clock pulse generator
Subclock pulse generator
Figure 4.1 Block Diagram of Clock Pulse Generators (H8/3802, H8/38004, H8/38002S Group)
CPG0201A_000020020900
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Section 4 Clock Pulse Generators
Internal reset signal (other than watchdog timer or low-voltage detect circuit reset) C
IRQAEC
D
Latch
Q
OSC/2 System clock divider OSC/16 OSC/32 OSC/64 OSC/128 Prescaler S (13 bits) /2 to /8192
OSC1 OSC2
System clock oscillator
OSC
(fOSC)
System clock divider (1/2)
On-chip oscillator
ROSC
System clock pulse generator
W W/2 X1 X2 Subclock oscillator W Subclock divider (1/2, 1/4, 1/8) W/4 W/8
(fW)
SUB W/2 W/4 Prescaler W (5 bits) W/8 to W/128
Subclock pulse generator
Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38104 Group) The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. The system clock is divided by prescaler S to become a clock signal from /8192 to /2, and the subclock is divided by prescaler W to become a clock signal from w/128 to w/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
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Section 4 Clock Pulse Generators
4.2
Register Description
Oscillator Control Register (OSCCR) (H8/38104 Group Only) OSCCR contains a flag indicating the selection status of the system clock oscillator and on-chip oscillator, indicates the input level of the IRQAEC pin during resets, and controls whether the subclock oscillator operates or not.
Bit 7 Bit Name SUBSTP Initial Value 0 R/W R/W Description Subclock oscillator stop control 0: Subclock oscillator operates 1: Subclock oscillator stopped Note: Bit 7 can be set to 1 only in the active mode (highspeed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to stop operating. 6 5 to 3 2 IRQAECF 0 All 0 R R/W R Reserved This bit is always read as 0 Reserved These bits are read/write enabled reserved bits. IRQAEC flag This bit indicates the IRQAEC pin input level set during resets. 0: IRQAEC pin set to GND during resets 1: IRQAEC pin set to VCC during resets 1 OSCF R OSC flag This bit indicates the oscillator operating with the system clock pulse generator. 0: System clock oscillator operating (on-chip oscillator stopped) 1: On-chip oscillator operating (system clock oscillator stopped) 0 0 R/W Reserved Never write 1 to this bit, as it can cause the LSI to malfunction.
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Section 4 Clock Pulse Generators
4.3
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 4.3 shows a block diagram of the system clock generator. As shown in figure 4.2, the H8/38104 Group supports selection between a system clock oscillator and an on-chip oscillator. See section 4.3.4, on-chip oscillator selection method, for information on selecting the on-chip oscillator.
OSC2
LPM OSC1 Note: LPM: Power-down mode (standby mode, subactive mode, subsleep mode, watch mode)
Figure 4.3 Block Diagram of System Clock Generator 4.3.1 Connecting Crystal Resonator
Figure 4.4(1) shows a typical method of connecting a crystal oscillator to the H8/3802 Group, and figure 4.4(2) shows a typical method of connecting a crystal oscillator to the H8/38004, H8/38104 and H8/38002S Group. Figure 4.5 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 4.1 should be used.
C1 OSC1 Rf OSC2 C2 Frequency Manufacturer C1, C2 Recommendation Value 12 pF 20% 4.19 MHz NIHON DEMPA KOGYO CO., LTD. C1 = C 2 = 12 pF 20% Rf = 1 M 20% Note: Consult with the crystal resonator manufacturer to determine the circuit constants.
Figure 4.4(1) Typical Connection to Crystal Resonator (H8/3802 Group)
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Section 4 Clock Pulse Generators
C1 OSC1 Rf OSC2 C2 4.0 MHz NIHON DEMPA KOGYO CO., LTD. Frequency Manufacturer Prodoct Name NR-18 C1, C2 Recommendation Value 12 pF 20%
Rf = 1 M 20% Note: Consult with the crystal resonator manufacturer to determine the circuit constants.
Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004, H8/38002S, H8/38104 Group)
LS RS
CS
OSC1 C0
OSC2
Figure 4.5 Equivalent Circuit of Crystal Resonator Table 4.1 Crystal Resonator Parameters
4.10 100 7 pF 4.193
Frequency (MHz) RS (max) C0 (max)
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Section 4 Clock Pulse Generators
4.3.2
Connecting Ceramic Resonator
Figure 4.6(1) shows a typical method of connecting a ceramic oscillator to the H8/3802 Group, and figure 4.6(2) shows a typical method of connecting a crystal oscillator to the H8/38004, H8/38002S and H8/38104 Group.
C1 OSC1 Rf OSC2 C1 = C 2 = 30 pF 10% Rf = 1 M 20% Note: Consult with the ceramic resonator manufacturer to determine the circuit constants. C2 Frequency 4.0 MHz Manufacturer Murata Manufacturing Co., Ltd. C1, C2 Recommendation Value 30 pF 10%
Figure 4.6(1) Typical Connection to Ceramic Resonator (H8/3802 Group)
C1 OSC1 Rf OSC2 Ceramic resonator Frequency C2 2.0 MHz Murata Manufacturing Co., CSTCC2M00G53-B0 Ltd. CSTCC2M00G56-B0
CSTLS10M0G53-B0 CSTLS10M0G56-B0
Manufacturer
Prodoct Name
C1, C2 Recommendation Value
15 pF 20% 47 pF 20% 15 pF 20% 47 pF 20% 15 pF 20% 15 pF 20%
10.0 MHz 16.0 MHz*1 20.0 MHz*2 Rf = 1 M 20%
CSTLS16M0X53-B0 CSTLS20M0X53-B0
Notes: Consult with the crystal resonator manufacturer to determine the circuit constants. 1. This does not apply to the H8/38004 and H8/38002S Group. 2. H8/38104 Group only.
Figure 4.6(2) Typical Connection to Ceramic Resonator (H8/38004, H8/38002S, H8/38104 Group)
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Section 4 Clock Pulse Generators
4.3.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.7 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
External clock input
OSC2
Open
Figure 4.7 Example of External Clock Input 4.3.4 On-Chip Oscillator Selection Method (H8/38104 Group Only)
The on-chip oscillator is selected by setting the IRQAEC pin input level during resets*. The IRQAEC pin input level set during resets must be fixed at VCC or GND, based on the oscillator to be selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip oscillator is selected. In this case, pin OSC1 should be fixed at VCC or GND. Notes: The system clock oscillator must be selected in order to program or erase flash memory as part of operations such as on-board programming. Also, when using the on-chip emulator, an oscillator should be connected, or an external clock input, even if the on-chip oscillator is selected. * Other than watchdog timer or low-voltage detect circuit reset. Table 4.2 System Clock Oscillator and On-Chip Oscillator Selection Methods
0 Enabled Disabled 1 Disabled Enabled
IRQAEC pin input level (during resets) System clock oscillator On-chip oscillator
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Section 4 Clock Pulse Generators
4.4
Subclock Generator
Figure 4.8 shows a block diagram of the subclock generator. Note that on the H8/38104 Group the subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR register. The register setting to disable the subclock oscillator should be made in the active mode. When restoring operation of the subclock oscillator after it has been disabled using the OSCCR register, it is necessary to wait for the oscillation stabilization time (typ = 8s) to elapse before using the subclock.
X2
10 M
X1 Note : Resistance is a reference value.
Figure 4.8 Block Diagram of Subclock Generator 4.4.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz or 38.4-kHz crystal resonator, as shown in figure 4.9. Figure 4.10 shows the equivalent circuit of the 32.768kHz or 38.4-kHz crystal resonator. Note that only operation at 32.768 kHz is guaranteed on the H8/38104 Group.
C1 X1 C2 X2
Frequency 38.4 kHz
Manufacturer Seiko Instruments Inc.
Product Name VTC-200 MX73P
32.768 kHz NIHON DEMPA KOGYO CO., LTD. C1 = C 2 = 6 to 12.5 pF (typ.) Note: Consult with the crystal resonator manufacturer to determine the circuit constants.
Figure 4.9 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator
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Section 4 Clock Pulse Generators
LS CS RS
X1 CO
X2
CO = 0.8 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz/38.4 kHz Note: Constants are reference values.
Figure 4.10 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator 4.4.2 Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure 4.11.
X1 GND X2 Open
Figure 4.11 Pin Connection when Not Using Subclock 4.4.3 External Clock Input
Connect the external clock to pin X1 and leave pin X2 open, as shown in figure 4.12. Note that input of an external clock is not supported on the H8/38104 Group.
X1
External clock input
X2
Open
Figure 4.12 Pin Connection when Inputting External Clock
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Section 4 Clock Pulse Generators Frequency Duty Subclock (w) 45% to 55%
4.5
4.5.1
Prescalers
Prescaler S
Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral function. In active (mediumspeed) mode and sleep mode, the clock input to prescaler S is determined by the division ratio designated by the MA1 and MA0 bits in SYSCR2. 4.5.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (W/4) as its input clock. The divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 in TMA.
4.6
4.6.1
Usage Notes
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. Design the circuit so that the resonator never receives voltages exceeding its maximum rating.
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Section 4 Clock Pulse Generators
PB3 X1 X2 Vss OSC2 OSC1 TEST
(Vss)
Figure 4.13 Example of Crystal and Ceramic Resonator Arrangement Figure 4.14 (1) shows an example of the measurement circuit for the negative resistor which is recommended by the resonator manufacturer. Note that if the negative resistor in this circuit does not reach the level which is recommended by the resonator manufacturer, the main oscillator may be hard to start oscillation. If the negative resistor does not reach the level which is recommended by the resonator manufacturer and oscillation is not started, changes as shown in figure 4.14 (2) to (4) should be made. The proposed change and capacitor size to be applied should be determined according to the evaluation result of the negative resistor and frequency deviation, etc.
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Section 4 Clock Pulse Generators
Change OSC1 C1
Rf
OSC1 C1
Rf
OSC2 C2 Negative resistor -R added (1) Negative resistor measurement circuit C2
OSC2
(2) Proposed Change in Oscillator Circuit 1
Change
Change OSC1 C1
Rf
C3 OSC1 C1
Rf
OSC2 C2 (3) Proposed Change in Oscillator Circuit 2 C2
OSC2
(4) Proposed Change in Oscillator Circuit 3
Figure 4.14 Negative Resistor Measurement and Proposed Changes in Circuit 4.6.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 4.15).
Avoid Signal A Signal B
C1 OSC1 C2 OSC2
Figure 4.15 Example of Incorrect Board Design
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Section 4 Clock Pulse Generators
4.6.3
Definition of Oscillation Stabilization Standby Time
Figure 4.16 shows the oscillation waveform (OSC2), system clock (), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with a resonator connected to the system clock oscillator. As shown in figure 4.16, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation stabilization time and standby time) is required. 1. Oscillation stabilization time (trc) The time from the point at which the oscillation waveform of the system clock oscillator starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. Standby time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. The standby time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in the system control register 1 (SYSCR1)).
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Section 4 Clock Pulse Generators
Oscillation waveform (OSC2)
System clock ()
Oscillation stabilization time
Standby time
Standby mode, Operating mode watch mode, or subactive mode
Oscillation stabilization standby time
Active (high-speed) mode or active (medium-speed) mode
Interrupt accepted
Figure 4.16 Oscillation Stabilization Standby Time When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. Therefore, when a resonator is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes--that is, the oscillation stabilization time--is required. The oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc " in the AC characteristics. Meanwhile, once the system clock has halted, a standby time is necessary in order for the CPU and peripheral functions to operate normally. Thus, the time required from interrupt generation until operation of the CPU and peripheral functions is the sum of the above described oscillation stabilization time and standby time. This total time is called the oscillation stabilization standby time, and is expressed by equation (1) below.
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Section 4 Clock Pulse Generators
Oscillation stabilization standby time = oscillation stabilization time + standby time = trc +(8 to 16,384 states) *1................. (1) (to 131,072 states) *2 Notes: 1. H8/3802 Group, H8/38004 and H8/38002S Group 2. H8/38104 Group Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with a resonator connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization standby time. In particular, since the oscillation settling time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the resonator manufacturer. 4.6.4 Notes on Use of Resonator
When a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual resonator characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer standby time. For example, if erroneous operation occurs with a standby time setting of 16 states, check the operation with a standby time setting of 1,024* states or more.
Note: * This figure applies to the H8/3802, H8/38004 and H8/38002S Groups. The number of states on the H8/38104 Group is 8,192 or more.
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SER
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the pin low for a longer period.
Section 4 Clock Pulse Generators
4.6.5
Notes on H8/38104 Group
When using the on-chip emulator, system clock precision is necessary for programming or erasing the flash memory. However, the on-chip oscillator frequency can vary due to changes in conditions such as voltage or temperature. Consequently, when using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an external clock should be supplied, if the on-chip oscillator is selected. In this case, the LSI uses the on-chip oscillator when user programs are being executed and the system clock oscillator when programming or erasing flash memory. The process is controlled by the on-chip emulator.
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Section 5 Power-Down Modes
Section 5 Power-Down Modes
This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. * Active (medium-speed) mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc/16, osc/32, osc/64, and osc/128. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Sleep (high-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Sleep (medium-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc/16, osc/32, osc/64, and osc/128. * Subsleep mode The CPU halts. The timer A, timer F, SCI3, AEC, and LCD controller/driver are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Watch mode The CPU halts. Timer A's timekeeping function, timer F, AEC, and LCD controller/driver are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode.
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Section 5 Power-Down Modes
5.1
Register Descriptions
The registers related to power-down modes are as follows. * System control register 1 (SYSCR1) * System control register 2 (SYSCR2) * Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2) 5.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Selects the mode to transit after the execution of the SLEEP instruction. 0: A transition is made to sleep mode or subsleep mode. 1: A transition is made to standby mode or watch mode. For details, see table 5.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, subsleep mode, or watch mode to active mode or sleep mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. The relationship between the specified value and the number of wait states is shown in tables 5.1(1) and 5.1(2). When an external clock is to be used, the minimum value (STS2 = 1, STS1 = 0, STS0 = 1) is recommended. 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38104 Group. If the setting other than the recommended value is made, operation may start before the end of the waiting time. 3 LSON 0 R/W Selects the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. 0: The CPU operates on the system clock () 1: The CPU operates on the subclock (SUB)
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Bit 2 1 0
Bit Name MA1 MA0
R/W R/W R/W
Description Reserved This bit is always read as 1 and cannot be modified. Active Mode Clock Select 1 and 0 Select OSC/16, OSC/32, OSC/64, or OSC/128 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. The MA1 and MA0 bits should be written to in active (high-speed) mode or subactive mode. 00: OSC/16 01: OSC/32 10: OSC/64 11: OSC/128
Table 5.1(1) Operating Frequency and Waiting Time (H8/3802 Group, H8/38004 Group, H8/38002S Group)
Bit STS2 0 STS1 0 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Waiting Time 8,192 states 16,384 states 1,024 states 2,048 states 4,096 states 2 states (external clock input) 8 states 16 states Operating Frequency 5 MHz 1.638 3.277 0.205 0.410 0.819 0.0004 0.002 0.003 2 MHz 4.1 8.2 0.512 1.024 2.048 0.001 0.004 0.008
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Table 5.1(2) Operating Frequency and Waiting Time (H8/38104 Group)
Bit STS2 0 STS1 0 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 2 states (external clock input) 8 states 16 states Operating Frequency 5 MHz 1.638 3.277 6.554 13.108 26.216 0.0004 0.002 0.003 2 MHz 4.1 8.2 16.4 32.8 65.5 0.001 0.004 0.008
Note: The time unit is ms. If external clock input is used, STS2 to STS0 should be set to the external clock input mode before the mode transition is executed. In addition, STS2 to STS0 should not be set to the external clock input mode if external clock input is not used. When the on-chip clock oscillator is used on the H8/38104 Group, a setting of 8,192 states (STS2 = STS1 = STS0 = 0) is recommended.
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5.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 NESEL 1 R/W Noise Elimination Sampling Frequency Select Selects the frequency at which the watch clock signal (W ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (OSC) generated by the system clock pulse generator. When OSC = 2 to 16 MHz, clear this bit to 0. 0: Sampling rate is OSC/16. 1: Sampling rate is OSC/4. 3 DTON 0 R/W Direct Transfer on Flag Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY and LSON in SYSCR1, bit MSON in SYSCR2, and bit TMA3 in TMA. For details, see table 5.2. 2 MSON 0 R/W Medium Speed on Flag After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: Operation in active (high-speed) mode 1: Operation in active (medium-speed) mode 1 0 SA1 SA0 0 0 R/W R/W Subactive Mode Clock Select 1 and 0 Select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W /8 01: W /4 1X: W /2 Legend: X: Don't care.
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5.1.3
Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2)
CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter a standby state in module units. * CKSTPR1
Bit 7, 6 5 Bit Name S32CKSTP Initial Value All 1 1 R/W R/W Description Reserved SCI Module Standby SCI3 enters standby mode when this bit is cleared to 0.*1 4 ADCKSTP 1 R/W A/D Converter Module Standby A/D converter enters standby mode when this bit is cleared to 0. 3 2 TFCKSTP 1 1 R/W Reserved Timer F Module Standby Timer F enters standby mode when this bit is cleared to 0. 1 0 TACKSTP 1 1 R/W Reserved Timer A Module Standby*2 Timer A enters standby mode when this bit is cleared to 0.
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* CKSTPR2
Bit 7 Bit Name LVDCKSTP Initial Value 1 R/W R/W Description LVD module standby The LVD module enters standby status when this bit is cleared to 0. Note: On products other than the H8/38104 Group, this bit is reserved like bits 6 and 5. 6, 5 4 All 1 R/W *3 Reserved PWM2 Module Standby PWM2 enters standby mode when this bit is cleared to 0. 3 AECKSTP 1 R/W Asynchronous Event Counter Module Standby Asynchronous event counter enters standby mode when this bit is cleared to 0 2 WDCKSTP 1 R/W *4 Watchdog Timer Module Standby Watchdog timer enters standby mode when this bit is cleared to 0 1 PW1CKSTP 1 R/W PWM1 Module Standby PWM1 enters standby mode when this bit is cleared to 0 0 LDCKSTP 1 R/W LCD Module Standby LCD controller/driver enters standby mode when this bit is cleared to 0 Notes: 1. When the SCI module standby is set, all registers in the SCI3 enter the reset state. 2. When the timer A module standby is set, the TMA3 bit in TMA cannot be rewritten. When the TMA3 bit is rewritten, the TACKSTP bit in CKSTPR1 should be set to 1 in advance. 3. This bit cannot be read or written in the H8/3802 Group. 4. This bit cannot be read or written in the H8/3802 Group. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer does not enter module standby mode and continues operating. When the watchdog timer stops operating and the WDON bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode. PW2CKSTP 1
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5.2
Mode Transitions and States of LSI
Figure 5.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. input enables transitions from a mode to the reset state. Table 5.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 5.3 shows the internal states of the LSI in each mode.
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Program execution state SLEEP d instruction 4 d SLEEP instruction g f SLEEP instruction 4 SLEEP instruction Active (high-speed mode) Program halt state Sleep (high-speed) mode
Reset state Program halt state Standby mode
SLEEP instruction a 3 a Pn EE ctio SL tru s in
Pn EE tio SL truc s in
b
SLEEP b instruction e SLEEP instruction 1 e
S ins LE tru EP cti on
Active (medium-speed) mode j SLEEP instruction i h SLEEP instruction SLEEP instruction i SLEEP instruction
3
Sleep (medium-speed) mode
1
Watch mode
e SLEEP instruction 1
Subactive mode
SLEEP instruction c Subsleep 2 mode
: Transition is made after exception handling is executed. Mode Transition Conditions (1) LSON a b c d e f g h i j 0 0 1 0 * 0 0 0 1 0 MSON SSBY 0 1 * * * 0 1 1 * 0 0 0 0 1 1 0 0 1 1 1 TMA3 * * 1 0 1 * * 1 1 1 DTON 0 0 0 0 0 1 1 1 1 1
3 4 2 1
Power-down modes
Mode Transition Conditions (2) Interrupt Sources
Timer A, Timer F, IRQ0 interrupt, WKP7 to WKP0 interrupts Timer A, Timer F, SCI3 interrupt, IRQ1 and IRQ0, IRQAEC interrupts, WKP7 o WKP0 interrupts, AEC All interrupts IRQ1 or IRQ0, WKP7 to WKP0 interrupts
Legend: * Don't care Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupts are enabled.
Figure 5.1 Mode Transition Diagram
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Table 5.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
Transition Mode after SLEEP Instruction Execution Transition Mode due to Interrupt
LSON 0 0 1 0 X 0 0 0 1 0
MSON 0 1 X X X 0 1 1 X 0
SSBY 0 0 0 1 1 0 0 1 1 1
TMA3 X X 1 0 1 X X 1 1 1
DTON 0 0 0 0 0 1 1 1 1 1
Sleep (high-speed) mode Active (high-speed) mode Sleep (medium-speed) mode Subsleep mode Standby mode Watch mode Active (medium-speed) mode Subactive mode Active mode Active mode, subactive mode
Active (high-speed) mode Active (medium-speed) mode Active (medium-speed) mode Subactive mode (direct transition)
Active (high-speed) mode (direct transition)
Legend: X: Don't care.
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Table 5.3
Internal State in Each Operating Mode
Active Mode Sleep Mode Medium- Watch speed Mode Functioning Functioning Halted Halted Functioning Halted Subactive Mode Halted Functioning Functioning
Function System clock oscillator Subclock oscillator CPU Instructions RAM Registers I/O External IRQ0 interrupts IRQ1
IRQAEC
Highspeed Functioning Functioning Functioning
Medium- Highspeed speed Functioning Functioning Functioning Functioning Functioning Halted
Subsleep Stand-by Mode Mode Halted Functioning Halted Halted Functioning Halted
Retained Retained Retained
Retained Retained
Re1 tained* Functioning Functioning Functioning Functioning Functioning Retained*5 Functioning Functioning Functioning
Retained*5 Functioning Func4 tioning * Functioning Func4 tioning * Functioning Retained Func6 tioning *
WKP7 to WKP0 Peripheral modules Timer A Asynchronous counter Timer F Functioning Functioning Functioning Functioning
Functioning Func4 tioning * Func6 tioning *
Function- Function- Function- Retained ing/reta- ing/reta- ing/reta7 7 7 ined* ined* ined* Function- Function- Function- Functioning/reta- ing/reta- ing/reta- ing/reta9 8 9 10 ined* ined* ined* ined* Functioning Functioning Functioning Functioning Reset Function- Function- Reset ing/reta- ing/reta2 2 ined* ined*
WDT
SCI3
PWM
Functioning
Functioning
Functioning
Functioning
Retained Retained Retained Retained
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Active Mode Function Peripheral modules A/D converter LCD Highspeed Functioning Functioning Functioning Sleep Mode Medium- Watch Mode speed Functioning Functioning Functioning Subactive Mode
Medium- Highspeed speed Functioning Functioning Functioning Functioning Functioning Functioning
Subsleep Stand-by Mode Mode
Retained Retained Retained Retained Function- Function- Function- Retained ing/reta- ing/reta- ing/reta3 3 3 ined* ined* ined* Functioning Functioning Functioning Functioning
LVD
Notes: 1. Register contents are retained. Output is the high-impedance state. 2. Functioning if W /2 is selected as an internal clock, or halted and retained otherwise. 3. Functioning if w, w/2, or w/4 is selected as a clock to be used. Halted and retained otherwise. 4. Functioning if the timekeeping time-base function is selected. 5. An external interrupt request is ignored. Contents of the interrupt request register are not affected. 6. The counter can be incremented. An interrupt cannot occur. 7. Functioning if w/4 is selected as an internal clock. Halted and retained otherwise. 8. On the H8/38104 Group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004, H8/38002S Group, operates when w/32 is selected as the internal clock; otherwise stops and stands by. 9. On the H8/38104 Group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004, H8/38002S Group, stops and stands by. 10. On the H8/38104 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004, H8/38002S Group, stops and stands by.
5.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed) mode to active (medium-speed) mode.
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When the pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started. Furthermore, it sometimes operates with half state early timing at the time of transition to sleep (medium-speed) mode. 5.2.2 Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2. Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. pin goes low, the system clock pulse generator starts. Since system clock signals When the are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the pin must be kept low until the pulse generator output stabilizes. After the pulse generator pin is driven high. output has stabilized, the CPU starts reset exception handling if the Watch Mode
5.2.3
In watch mode, the system clock oscillator and CPU operation stop and on-chip peripheral modules stop functioning except for the timer A, timer F, asynchronous event counter, and LCD controller/driver. However, as long as the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain their state before the transition. Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
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Section 5 Power-Down Modes
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. pin goes low, the system clock pulse generator starts. Since system clock signals When the are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the pin must be kept low until the pulse generator output stabilizes. After the pulse generator pin is driven high. output has stabilized, the CPU starts reset exception handling if the 5.2.4 Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the A/D converter and PWM function. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. pin goes low, the system clock pulse generator starts. Since system clock signals When the are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the pin must be kept low until the pulse generator output stabilizes. After the pulse generator pin is driven high. output has stabilized, the CPU starts reset exception handling if the 5.2.5 Subactive Mode
In subactive mode, the system clock oscillator stops but on-chip peripheral modules other than the A/D converter and PWM function. As long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits SSBY and LSON in SYSCR1, bits MSON and DTON in SYSCR2, and bit TMA3 in TMA. Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. pin goes low, the system clock pulse generator starts. Since system clock signals When the are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the pin is driven high.
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Section 5 Power-Down Modes
The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. 5.2.6 Active (Medium-Speed) Mode
In active (medium-speed) mode, the system clock oscillator, subclock oscillator, CPU, and on-chip peripheral modules function. Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY and LSON in SYSCR1 and bit TMA3 in TMA, a transition to watch mode is made depending on the combination of bit SSBY in SYSCR1 and bit TMA3 in TMA, or a transition to sleep mode is made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. Active (mediumsleep) mode is not entered if the I bit in CCR is set to 1 or the requested interrupt is disabled in the pin goes low, the CPU goes into the reset state and active interrupt enable register. When the (medium-sleep) mode is cleared. Furthermore, it sometimes operates with half state early timing at the time of transition to active (medium-speed) mode. In active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1.
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5.3
Direct Transition
The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts. If the direct transition interrupt is disabled in interrupt permission register 2, a transition is made instead to sleep or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep or watch mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. * Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. * Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. * Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. * Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
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* Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} * (tcyc before transition) + (Number of interrupt exception handling execution states) * (tcyc after transition) .....................(1) Example: Direct transition time = (2 + 1) * 2tosc + 14 * 16tosc = 230tosc (when /8 is selected as the CPU operating clock)
Legend: tosc: OSC clock cycle time tcyc: System clock () cycle time
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5.3.2
Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} * (tcyc before transition) + (Number of interrupt exception handling execution states) * (tcyc after transition) ....................(2) Example: Direct transition time = (2 + 1) * 16tosc + 14 * 2tosc = 76tosc (when /8 is selected as the CPU operating clock)
Legend: tosc: OSC clock cycle time tcyc: System clock () cycle time 5.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} * (tsubcyc before transition) + {(Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states)} * (tcyc after transition) ....................(3) Example: Direct transition time = (2 + 1) * 8tw + (8192 + 14) * 2tosc = 24tw + 16412tosc (when w/8 is selected as the CPU operating clock and wait time = 8192 states)
Legend: tosc: tw: tcyc: tsubcyc:
OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time
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5.3.4
Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} * (tsubcyc before transition) + {(Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states)} * (tcyc after transition) ....................(4) Example: Direct transition time = (2 + 1) * 8tw + (8192 + 14) * 16tosc = 24tw + 131296tosc (when w/8 or /8 is selected as the CPU operating clock and wait time = 8192 states)
Legend: tosc: tw: tcyc: tsubcyc: 5.3.5
OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time
Notes on External Input Signal Changes before/after Direct Transition
* Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode.
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5.4
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section 5.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).)
5.5
5.5.1
Usage Notes
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows the timing in this case.
Internal data bus
SLEEP instruction fetch
Next instruction fetch Internal processing High-impedance Standby mode
SLEEP instruction execution Pins Port output
Active (high-speed) mode or active (medium-speed) mode
Figure 5.2 Standby Mode Transition and Pin States 5.5.2 Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode , , or IRQAEC is input, both the high- and When an external input signal such as low-level widths of the signal must be at least two cycles of system clock or subclock SUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in 3, Recommended timing of external input signals, below.
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PKW QRI
Section 5 Power-Down Modes
2. When external input signals cannot be captured because internal clock stops The case of falling edge capture is shown in figure 5.3. As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc. 3. Recommended timing of external input signals To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
Wait for oscillation stabilization
Operating mode
Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc
Standby mode or watch mode tcyc tsubcyc
Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc
or SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal
Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode 4. Input pins to which these notes apply: , , to , and IRQAEC
0 PKW 7 P KW 0QRI 1QRI
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Section 5 Power-Down Modes
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Section 6 ROM
Section 6 ROM
The H8/3802 has 16 kbytes of the on-chip mask ROM, the H8/3801 has 12 kbytes, and the H8/3800 has 8 kbytes. The H8/38004 and H8/38104 have 32 kbytes of the on-chip mask ROM, the H8/38003 and H8/38103 have 24 kbytes, the H8/38002, H8/38002S and H8/38102 have 16 kbytes, the H8/38001, H8/38001S and H8/38101 have 12 kbytes, and the H8/38000, H8/38000S and H8/38100 have 8 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. The H8/3802 has a ZTAT version with 16-kbyte PROM. The H8/38004, H8/38002, H8/38104, and H8/38102 have F-ZTATTM versions with 32-kbyte flash memory and 16-kbyte flash memory, respectively.
6.1
Block Diagram
Figure 6.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000 H'0002
H'0000 H'0002
H'0001 H'0003
On-chip ROM H'3FFE H'3FFE Even address H'3FFF Odd address
Figure 6.1 Block Diagram of ROM (H8/3802)
ROM3322A_000020020900
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Section 6 ROM
6.2
6.2.1
H8/3802 PROM Mode
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcomputer and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set the chip to PROM mode. Table 6.1
Pin Name TEST PB0/AN0 PB1/AN1 PB2/AN2 High level
Setting to PROM Mode
Setting High level Low level
6.2.2
Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 32 pins. Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.
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Section 6 ROM
H8/3802 FP-64A, FP-64E 8 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 60 30 29 28 27 26 52 53 25 31 51 16 61 7 2 64 49 50 54 55 4 62 63 DP-64S 16 48 47 46 45 44 43 42 41 1 2 18 19 20 21 22 23 40 4 38 37 36 35 34 60 61 33 39 59 24 5 15 10 8 57 58 62 63 12 6 7 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P43 P72 P73 P74 P75 P76 P93 P94 P77 P71 P92 VCC AVCC TEST X1 PB2 P90 P91 P95 VSS AVSS PB0 PB1 VSS 16 VCC Pin EPROM socket Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16
HN27C101 (32 pins)
1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32
Note: Pins not shown in the figure should be open.
Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)
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Section 6 ROM
Address in MCU mode H'0000 Address in PROM mode H'0000
On-chip PROM
H'3FFF Uninstalled area*
H'3FFF
H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'3FFF. If programming is inadvertently performed from H'4000 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in this address area (H'4000 to H'1FFFF).
Figure 6.3 H8/3802 Memory Map in PROM Mode
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Section 6 ROM
6.3
H8/3802 Programming
The write, verify, and other modes are selected as shown in table 6.2 in H8/3802 PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/3802)
Pins Mode Write Verify Programming disabled Vpp Vpp Vpp Vpp Vcc Vcc Vcc Vcc EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input
L L L L H H
H L L H L H
H L H L H
Legend: L: Low level H: High level Vpp: Vpp level Vcc: Vcc level
The specifications for writing and reading are identical to those for the standard HN27C101 EPROM. However, page programming is not supported, and so page programming mode must not be set. A PROM programmer that only supports page programming mode cannot be used. When selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. Also, be sure to specify addresses from H'0000 to H'3FFF. 6.3.1 Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. The basic flow of this high-speed, high-reliability programming method is shown in figure 6.4.
MGP
L
EO
EC
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Section 6 ROM
Start
Set write/verify mode VCC = 6.0 V0.25 V, VPP = 12.5 V0.3 V
Address = 0
n=0
n+1n Yes No n < 25 Write time tpw = 0.2 ms5%
No
Verify Yes Write time topw = 0.2n ms
Address + 1 address
Last address? Yes Set read mode VCC = 5.0 V0.25 V, VPP = VCC
No
Error
No
Read all addresses? Yes End
Figure 6.4 High-Speed, High-Reliability Programming Flowchart Table 6.3 and table 6.4 give the electrical characteristics in programming mode.
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Section 6 ROM
Table 6.3
DC Characteristics
(Conditions: Vcc = 6.0 V 0.25 V, Vpp = 12.5 V 0.3 V, Vss = 0 V, Ta = 25C 5C)
Item Input highlevel voltage EO7 to EO0, EA16 to EA0, , , Symbol VIH Min 2.4 Typ -- Max Vcc + 0.3 Unit V Test Condition
Output highlevel voltage Output lowlevel voltage Input leakage current Vcc current Vpp current
MGP EC EO
EO7 to EO0 EO7 to EO0 EO7 to EO0, EA16 to EA0, , ,
Input low-level EO7 to EO0, voltage EA16 to EA0, , ,
MGP EC EO MGP EC EO
VIL
-0.3
--
0.8
V
VOH VOL | ILI |
2.4 -- --
-- -- --
-- 0.45 2
V V A
IOH = -200 A IOL = 0.8 mA Vin = 5.25 V/0.5 V
ICC IPP
-- --
-- --
40 40
mA mA
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Section 6 ROM
Table 6.4
AC Characteristics
(Conditions: Vcc = 6.0 V 0.25 V, Vpp = 12.5 V 0.3 V, Ta = 25C 5C)
Item Address setup time setup time Symbol tAS tOES tDS tAH tDH tDF*2 tVPS tPW tOPW *3 tCES tVCS tOE Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 200 Unit s s s s s s s ms ms s s ns Test Condition Figure 6.5*1
Notes: 1. Input pulse level: 0.45 V to 2.4 V Input rise time/fall time 20 ns Timing reference levels Input: 0.8 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined at the point at which the output is floating and the output level cannot be read. 3. tOPW is defined by the value given in figure 6.4, High-Speed, High-Reliability Programming Flow Chart.
Figure 6.5 shows a PROM write/verify timing.
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MGP
EO EC
Data setup time Address hold time Data hold time Data output disable time Vpp setup time Programming pulse width pulse width for overwrite programming setup time
Vcc setup time Data output delay time
Section 6 ROM
Write Address Verify
tAS Data tDS VPP VPP VCC tVPS Input data tDH Output data
tAH
tDF
VCC
VCC+1 VCC tVCS
tCES
tPW
tOES
tOE
tOPW*
Note: * tOPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing 6.3.2 Programming Precautions
* Use the specified programming voltage and timing. The programming voltage in PROM mode (Vpp) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas (former Hitachi) specifications for the HN27C101 will result in correct Vpp of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer. * Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors.
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Section 6 ROM
* Take care when setting the programming mode, as page programming is not supported. * When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'3FFF. If programming is inadvertently performed from H'4000 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in address area H'4000 to H'1FFFF.
6.4
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 6.6 shows the recommended screening procedure.
Program chip and verify programmed data
Bake chip for 24 to 48 hours at 125C to 150C with power off
Read and check program
Install
Figure 6.6 Recommended Screening Procedure If a Group of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
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Section 6 ROM
6.5
6.5.1
Overview of Flash Memory
Features
The features of the 32-kbyte or 16-kbyte flash memory built into the flash memory version are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory of the HD64F38004 and HD64F38104 are configured as follows: 1 kbyte x 4 blocks and 28 kbytes x 1 block. The flash memory of the HD64F38002 and HD64F38102 are configured as follows: 1 kbyte x 4 blocks and 12 kbytes x 1 block. To erase the entire flash memory, each block must be erased in turn. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption. Note: The system clock oscillator must be used when programming or erasing the flash memory of the HD64F38104 and HD64F38102.
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Section 6 ROM
6.5.2
Block Diagram
Internal address bus
Internal data bus (16 bits)
FLMCR1 FLMCR2
Module bus
Bus interface/controller EBR FLPWCR FENR
Operating mode
TEST pin P95 pin P34 pin
Flash memory
Legend: FLMCR1: FLMCR2: EBR: FLPWCR: FENR:
Flash memory control register 1 Flash memory control register 2 Erase block register Flash memory power control register Flash memory enable register
Figure 6.7 Block Diagram of Flash Memory
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Section 6 ROM
6.5.3
Block Configuration
Figure 6.8 shows the block configuration of 32-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 32kbyte flash memory is divided into 1 kbyte x 4 blocks and 28 kbytes x 1 block. Erasing is performed in these units. The 16-kbyte flash memory is divided into 1 kbyte x 4 blocks and 12 kbytes x 1 block. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
H'0000 Erase unit 1 kbyte H'0380 H'0400 Erase unit 1 kbyte H'0780 H'0800 Erase unit 1 kbyte H'0B80 H'0C00 Erase unit 1 kbyte H'0F80 H'1000 Erase unit 28 kbytes H'1080 H'0C80 H'0880 H'0480 H'0080
H'0001 H'0081
H'0002 H'0082
Programming unit: 128 bytes
H'007F H'00FF
H'0381 H'0401 H'0481
H'0382 H'0402 H'0482 Programming unit: 128 bytes
H'03FF H'047F H'04FF
H'0781 H'0801 H'0881
H'0782 H'0802 H'0882 Programming unit: 128 bytes
H'07FF H'087F H'08FF
H'0B81 H'0C01 H'0C81
H'0B82 H'0C02 H'0C82 Programming unit: 128 bytes
H'0BFF H'0C7F H'0CFF
H'0F81 H'1001 H'1081
H'0F82 H'1002 H'1082 Programming unit: 128 bytes
H'0FFF H'107F H'10FF
H'7F80
H'7F81
H'7F82
H'7FFF
Figure 6.8(1) Block Configuration of 32-kbyte Flash Memory
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Section 6 ROM
H'0000 Erase unit 1 kbyte H'0380 H'0400 Erase unit 1 kbyte H'0780 H'0800 Erase unit 1 kbyte H'0B80 H'0C00 Erase unit 1 kbyte H'0F80 H'1000 Erase unit 12 kbytes H'1080 H'0C80 H'0880 H'0480 H'0080
H'0001 H'0081
H'0002 H'0082
Programming unit: 128 bytes
H'007F H'00FF
H'0381 H'0401 H'0481
H'0382 H'0402 H'0482 Programming unit: 128 bytes
H'03FF H'047F H'04FF
H'0781 H'0801 H'0881
H'0782 H'0802 H'0882 Programming unit: 128 bytes
H'07FF H'087F H'08FF
H'0B81 H'0C01 H'0C81
H'0B82 H'0C02 H'0C82 Programming unit: 128 bytes
H'0BFF H'0C7F H'0CFF
H'0F81 H'1001 H'1081
H'0F82 H'1002 H'1082 Programming unit: 128 bytes
H'0FFF H'107F H'10FF
H'3F80
H'3F81
H'3F82
H'3FFF
Figure 6.8(2) Block Configuration of 16-kbyte Flash Memory
6.6
Register Descriptions
The flash memory has the following registers. * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register (EBR) Flash memory power control register (FLPWCR) Flash memory enable register (FENR)
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Section 6 ROM
6.6.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash Memory Programming/Erasing.
Bit 7 6 Bit Name -- SWE Initial Value 0 0 R/W -- R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, flash memory programming/erasing is invalid. Other FLMCR1 bits and all EBR bits cannot be set. Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. Erase When this bit is set to 1, and while the SWE = 1 and ESU = 1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. Program When this bit is set to 1, and while the SWE = 1 and PSU = 1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
5
ESU
0
R/W
4
PSU
0
R/W
3
EV
0
R/W
2
PV
0
R/W
1
E
0
R/W
0
P
0
R/W
Note: Bits SWE, PSU, EV, PV, E, and P should not be set at the same time. Rev. 6.00 Mar 15, 2005 page 145 of 502 REJ09B0024-0600
Section 6 ROM
6.6.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When flash memory goes to the error-protection state, this bit is set to 1. See section 6.9.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
6.6.3
Erase Block Register (EBR)
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0.
Bit 7 to 5 4 Bit Name -- EB4 Initial Value All 0 0 R/W -- R/W Description Reserved These bits are always read as 0. When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased in the HD64F38004 and HD64F38104. When this bit is set to 1, 12 kbytes of H'1000 to H'3FFF will be erased in the HD64F38002 and HD64F38102. 3 2 1 0 EB3 EB2 EB1 EB0 0 0 0 0 R/W R/W R/W R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will be erased. When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will be erased. When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will be erased. When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will be erased.
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Section 6 ROM
6.6.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
6.6.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and FLPWCR.
Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
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Section 6 ROM
6.7
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, P95 pin settings, and input level of each port, as shown in table 6.5. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 6.5
TEST 0 0 1
Setting Programming Modes
P95 1 0 X P34 X 1 X PB0 X X 0 PB1 X X 0 PB2 X X 0 LSI State after Reset End User Mode Boot Mode Programmer Mode
Legend: X: Don't care.
6.7.1
Boot Mode
Table 6.6 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 6.8, Flash Memory Programming/Erasing. 2. The SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. Since the inversion function of SPCR is configured not to inverse data of the TXD pin and RXD pin, do not place an inversion circuit between the host and this LSI. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
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Section 6 ROM
4.
5.
6.
7.
8.
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 6.7. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a WDT overflow occurs. Do not change the TEST pin and P95 pin input levels in boot mode.
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Section 6 ROM
Table 6.6
Item
Boot Mode Operation
Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start.
Boot mode initiation
Boot program initiation
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00 H'55
* Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication.
Flash memory erase
Boot program erase error
H'FF
H'AA reception
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.)
Transfer of number of bytes of programming control program
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte)
Upper bytes, lower bytes Echoback
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times)
H'XX Echoback
Echobacks received data to host and also transfers it to RAM. (repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program transferred to on-chip RAM and starts execution.
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Section 6 ROM
Table 6.7
Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible (fOSC)
Host Bit Rate 4,800 bps 2,400 bps 1,200 bps Oscillation Frequency Range of LSI (fOSC) 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz 16 to 20 MHz 8 to 20 MHz 4 to 20 MHz 2 to 20 MHz 2 to 20 MHz
Product Group H8/38004F Group
H8/38104F Group
19,200 bps 9,600 bps 4,800 bps 2,400 bps 1,200 bps
6.7.2
Programming/Erasing in User Program Mode
User program mode means the execution state of the user program. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 6.9 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 6.8, Flash Memory Programming/Erasing.
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Section 6 ROM
Reset-start
No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program
Branch to user program/erase control program in RAM
Execute user program/erase control program (flash memory rewrite)
Branch to flash memory application program
Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode 6.7.3 Notes on On-Board Programming
1. You must use the system clock oscillator when programming or erasing flash memory on the H8/38104F Group. The on-chip oscillator should not be used for programming or erasing flash memory. See section 4.3.4, On-Chip Oscillator Selection Method, for information on switching between the system clock oscillator and the on-chip oscillator. 2. On the H8/38104F Group the watchdog timer operates after a reset is canceled. When executing a program prepared by the user that performs programming and erasing in the user mode, the watchdog timer's overflow cycle should be set to an appropriate value. Refer to section 6.8.1, Program/Program-Verify, for information on the appropriate watchdog timer overflow cycle for programming, and to 6.8.2, Erase/Erase-Verify, for information on the appropriate watchdog timer overflow cycle for erasing.
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Section 6 ROM
6.8
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2, Erase/Erase-Verify, respectively. 6.8.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 6.8, and additional programming data computation according to table 6.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 6.10 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower one bit is B'0. Verify data can be read in word units from the address to which a dummy write was performed.
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Section 6 ROM
8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
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Section 6 ROM
Write pulse application subroutine
Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s
Disable WDT
START Set SWE bit in FLMCR1 Wait 1 s
Store 128-byte program data in program data area and reprogram data area
n1 m0
Write 128-byte data in RAM reprogram data area consecutively to flash memory
Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address
nn+1 H'FF dummy write to verify address
End Sub
Wait 2 s
Read verify data Increment address Verify data = write data?
No m1 No
Yes n6?
Yes Additional-programming data computation
Reprogram data computation
No
128-byte data verification completed?
Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse No Yes No
m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s
End of programming
n 1000 ?
No Clear SWE bit in FLMCR1 Wait 100 s
Programming failure
Figure 6.10 Program/Program-Verify Flowchart
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Section 6 ROM
Table 6.8
Reprogram Data Computation Table
Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit -- Remains in erased state
Program Data 0 0 1 1
Table 6.9
Additional-Program Data Computation Table
Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming
Reprogram Data 0 0 1 1
Table 6.10 Programming Time
n Programming (Number of Writes) Time 1 to 6 7 to 1,000 30 200 In Additional Programming 10 -- Comments
Note: Time shown in s.
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Section 6 ROM
6.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit is B'0. Verify data can be read in word units from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 6.8.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
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Section 6 ROM
Erase start SWE bit 1 Wait 1 s n1 Set EBR Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 0 Wait 10 s Disable WDT EV bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address Wait 2 s Read verify data No Increment address Verify data = all 1s ? Yes nn+1
No Last address of block ? Yes EV bit 0 Wait 4 s EV bit 0 Wait 4s
No
All erase block erased ? Yes
n 100 ? No
Yes
SWE bit 0 Wait 100 s End of erasing
SWE bit 0 Wait 100 s Erase failure
Figure 6.11 Erase/Erase-Verify Flowchart
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Section 6 ROM
6.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 pin, the reset (FLMCR2), and erase block register (EBR) are initialized. In a reset via the state is not entered unless the pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the pin low for the pulse width specified in the AC Characteristics section. 6.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00, erase protection is set for all blocks. 6.9.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered
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SER
SER
SER
SER
Section 6 ROM
by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset.
6.10
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-kbyte flash memory (FZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to programmer mode, see table 6.5. 6.10.1 Socket Adapter
The socket adapter converts the pin allocation of the HD64F38004, HD64F38002, HD64F38104, and HD64F38102 to that of the discrete flash memory HN28F101. The address of the on-chip flash memory is H'0000 to H'7FFF. Figure 6.12(1) shows a socket-adapter-pin correspondence diagram of the HD64F38004 and HD64F38002. Figure 6.12(2) shows a socket-adapter-pin correspondence of the HD64F38104 and HD64F38102. 6.10.2 Programmer Mode Commands
The following commands are supported in programmer mode. * * * * Memory Read Mode Auto-Program Mode Auto-Erase Mode Status Read Mode
Status polling is used for auto-programming, auto-erasing, and status read modes. In status read mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.11 shows the sequence of each command. In auto-programming mode, 129 cycles are required since 128 bytes are written at the same time. In memory read mode, the number of cycles depends on the number of address write cycles (n).
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Section 6 ROM
Table 6.11 Command Sequence in Programmer Mode
Command Name Memory read Autoprogram Number of Cycles Mode 1+n 129 Write Write Write Write 1st Cycle Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71
Auto-erase 2 Status read 2
Legend: n: Number of address write cycles
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Section 6 ROM
H8/38004F, H8/38002F Pin No. FP-64A FP-64E 31 25 49 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 59 30 29 28 27 26 60 16 61 2 7 17 50 54 4 55 62 63 64 6, 5 8 Other than above Pin Name
Socket Adapter (Conversion to 32-Pin Arrangement)
HN28F101 (32 Pins) Pin Name FWE Pin No. 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16
P71 P77 P90 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P42 P72 P73 P74 P75 P76 P43 Vcc AVcc X1 TEST V1 P91 P95 Vss Vss PB0 PB1 PB2 OSC1,OSC2 RES (OPEN) Oscillator circuit Power-on reset circuit
A9 A16 A15 WE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE Vcc Vss Legend: FWE: I/O7 to I/O0: A16 to A0: CE: OE: WE:
Flash-write enable Data input/output Address input Chip enable Output enable Write enable
Note: The oscillation frequency of the oscillator circuit should be 10 MHz.
Figure 6.12(1) Socket Adapter Pin Correspondence Diagram (H8/38004F, H8/38002F)
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Section 6 ROM
H8/38104F, H8/38102F Pin No. FP-64A FP-64E 31 25 49 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 59 30 29 28 27 26 60 16 61 2 7 17 50 53, 54 4 55 62 63 64 6, 5 8 Other than above Pin Name
Socket Adapter (Conversion to 32-Pin Arrangement)
HN28F101 (32 Pins) Pin Name FWE Pin No. 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16
P71 P77 P90 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P42 P72 P73 P74 P75 P76 P43 Vcc AVcc X1 TEST V1 P91 CVcc, P95 Vss Vss PB0 PB1 PB2 OSC1,OSC2 RES (OPEN) Oscillator circuit Power-on reset circuit
A9 A16 A15 WE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE Vcc Vss Legend: FWE: I/O7 to I/O0: A16 to A0: CE: OE: WE:
Flash-write enable Data input/output Address input Chip enable Output enable Write enable
Note: The oscillation frequency of the oscillator circuit should be 10 MHz.
Figure 6.12(2) Socket Adapter Pin Correspondence Diagram (H8/38104F, H8/38102F)
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Section 6 ROM
6.10.3
Memory Read Mode
After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed. 1. In memory read mode, command writes can be performed in the same way as in the command wait state. 2. After powering on, memory read mode is entered. 3. Tables 6.12 to 6.14 show the AC characteristics. Table 6.12 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Test Condition Figure 6.13
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EW EW
EC EC
Data hold time Data setup time Write pulse width rise time fall time
Section 6 ROM
Command write A15 to A0 tces tceh tnxtc Memory read mode Address stable
twep tf tr
tds I/O7 to I/O0
tdh
Note: Data is latched on the rising edge of
.
Figure 6.13 Timing Waveforms for Memory Read after Command Write Table 6.13 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Test Condition Figure 6.14
EW EW
EC EC
Data hold time Data setup time Write pulse width rise time fall time
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Section 6 ROM
Memory read mode A15 to A0 Address stable tnxtc tces tceh Other mode command write
tf
twep
tr
tds I/O7 to I/O0
tdh
Note: Do not enable
and
at the same time.
Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 6.14 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Access time output delay time output delay time Symbol tacc tce toe tdf toh Min -- -- -- -- 5 Max 20 150 150 100 -- Unit s ns ns ns ns Test Condition Figures 6.15 and 6.16
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EO
EC
EO EC
Output disable delay time Data output hold time
A15 to A0
Address stable
Address stable
tacc toh I/O7 to I/O0
tacc toh
Figure 6.15 Timing Waveforms in
and
Enable State Read
Section 6 ROM
A15 to A0
Address stable tce
Address stable tce
toe
toe
tacc I/O7 to I/O0
tacc toh tdf
toh
tdf
6.10.4
Auto-Program Mode
1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 4. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 5. Memory address transfer is performed in the second cycle (figure 6.17). Do not perform transfer after the third cycle. 6. Do not perform a command write during a programming operation. 7. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . 10. Table 6.15 shows the AC characteristics.
Rev. 6.00 Mar 15, 2005 page 167 of 502 REJ09B0024-0600
EC
EO
EC
Figure 6.16 Timing Waveforms in
and
Clock System Read
EO
Section 6 ROM
Table 6.15 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep twsts tas tah twrite tr tf Min 20 0 0 50 50 70 1 -- 0 60 1 -- -- Max -- -- -- -- -- -- -- 150 -- -- 3000 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns Test Condition Figure 6.17
I/O5 to I/O0
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EW EW
EC EC
Data hold time Data setup time Write pulse width Status polling start time
Status polling access time tspa Address setup time Address hold time Memory write time rise time fall time
A15 to A0 tces tceh tnxtc
Address stable tnxtc
tf
twep
tr
tas
tah Data transfer 1 to 128 bytes
twsts
tspa
tds I/O7
tdh
twrite
Write operation end decision signal I/O6 Write normal end decision signal H'40 H'00
Figure 6.17 Timing Waveforms in Auto-Program Mode
Section 6 ROM
6.10.5
Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . 5. Table 6.16 shows the AC characteristics. Table 6.16 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tests terase tr tf Min 20 0 0 50 50 70 1 -- 100 -- -- Max -- -- -- -- -- -- -- 150 40000 30 30 Unit s ns ns ns ns ns ms ns ms ns ns Test Condition Figure 6.18
Data hold time Data setup time Write pulse width Status polling start time
Status polling access time tspa Memory erase time rise time fall time
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EC
EO
EW EW
EC EC
Section 6 ROM
A15 to A0 tces tceh tnxtc tnxtc
tf
twep
tr
tests
tspa
tds I/O7
tdh
terase Erase end decision signal
I/O6 Erase normal end decision signal I/O5 to I/O0 H'20 H'20 H'00
Figure 6.18 Timing Waveforms in Auto-Erase Mode 6.10.6 Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than command write in status read mode is executed. 3. Table 6.17 shows the AC characteristics and table 6.18 shows the return codes.
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Section 6 ROM
Table 6.17 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Symbol Min 20 0 0 50 50 70 -- -- -- -- -- Max -- -- -- -- -- -- 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns Test Condition Figure 6.19
Read time after command tnxtc write hold time setup time tceh tces tdh tds twep toe tdf tce tr tf
I/O7 to I/O0
EW EW EC
EO
EC EC
Data hold time Data setup time Write pulse width output delay time
Disable delay time output delay time rise time fall time
A15 to A0 tces tceh tnxtc tces tceh tnxtc tnxtc
tce twep twep
tf
tr
tf
tr
toe
tds H'71
tdh
tds H'71
tdh
tdf
Note: I/O2 and I/O3 are undefined.
Figure 6.19 Timing Waveforms in Status Read Mode
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Section 6 ROM
Table 6.18 Return Codes in Status Read Mode
Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Initial Value 0 0 0 0 0 0 0 0 Description 1: Abnormal end 0: Normal end 1: Command error 0: Otherwise 1: Programming error 0: Otherwise 1: Erasing error 0: Otherwise Undefined Undefined 1: Over counting of writing or erasing 0: Otherwise 1: Effective address error 0: Otherwise
6.10.7
Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 6.19 Status Polling Output
I/O7 0 1 1 0 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 Status During internal operation Abnormal end Normal end --
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Section 6 ROM
6.10.8
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 6.20 Stipulated Transition Times to Command Wait State
Item Symbol Min 10 5 tbmv tdwn 10 0 Max -- -- -- -- Unit ms ms ms ms Test Condition Figure 6.20
Oscillation stabilization time tosc1 (crystal resonator) Oscillation stabilization time (ceramic resonator) Programmer mode setup time VCC hold time
tosc1
VCC
tbmv
Auto-program mode Auto-erase mode
tdwn
Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 6.10.9 Notes on Memory Programming
1. When performing programming using programmer mode on a chip that has been programmed/erased in on-board programming mode, auto-erasing is recommended before carrying out auto-programming. 2. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
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Section 6 ROM
6.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 6.21 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. Table 6.21 Flash Memory Operating States
Flash Memory Operating State LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode Watch mode PDWND = 0 (Initial value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode Standby mode PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode Standby mode
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Section 7 RAM
Section 7 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification Flash memory version H8/38004 H8/38002 H8/38104 H8/38102 PROM version Mask ROM version H8/3802 H8/3802 H8/3801 H8/3800 H8/38004 H8/38003 H8/38002 H8/38001 H8/38000 H8/38002S H8/38001S H8/38000S H8/38104 H8/38103 H8/38102 H8/38101 H8/38100 RAM Size 1 kbyte 1 kbyte 1 kbyte 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes RAM Address H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F
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Section 7 RAM
7.1
Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80 H'FB82
H'FB80 H'FB82
H'FB81 H'FB83
On-chip RAM H'FF7E H'FF7E Even address H'FF7F Odd address
Figure 7.1 Block Diagram of RAM (H8/3802)
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Section 8 I/O Ports
Section 8 I/O Ports
This LSI is provided with three 8-bit I/O ports, one 7-bit I/O port, one 4-bit I/O port, one 3-bit I/O port, one 1-bit I/O port, one 4-bit input-only port, one 1-bit input-only port, and one 6-bit outputonly port. Each port is configured by the port control register (PCR) that controls input and output, and the port data register (PDR) that stores output data. Input or output can be assigned to individual bits. Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable in 4-bit units. See section 2.9.4, Bit Manipulation Instructions, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in Appendix B, I/O Port Block Diagrams. Table 8.1 lists the functions of each port. Table 8.1 Port Functions
Function Switching Registers
Port Port 3
Description * * * 7-bit I/O port Input pull-up MOS option Large-current port*
1
Pins P37/AEVL P36/AEVH P35 P34 P33 P32/TMOFH P31/TMOFL
Other Functions
PMR3 Asynchronous event counter event inputs AEVL, AEVH
Timer F output compare output External interrupt 0 SCI3 data output (TXD32), data input (RXD32), clock input/output (SCK32) Wakeup input (WKP7 to ), segment output (SEG8 to SEG1)
0PKW
PMR3 PMR2 SCR3 SMR PMR5 LPCR
Port 4
* *
1-bit input-only port 3-bit I/O port
P43/IRQ0 P42/TXD32 P41/RXD32 P40/SCK32 P57 to P50/ to / SEG8 to SEG1
7PKW 0PKW
Port 5
* *
8-bit I/O port Input pull-up MOS option
Port 6
* *
8-bit I/O port Input pull-up MOS option 8-bit I/O port
P67 to P60/ SEG16 to SEG9 P77 to P70/ SEG24 to SEG17
Segment output (SEG16 to LPCR SEG9) Segment output (SEG24 to LPCR SEG17)
Port 7
*
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Section 8 I/O Ports Function Switching Registers LPCR (LVDSR)*3 PMR9
Port Port 8 Port 9
Description * * * 1-bit I/O port 6-bit output-only port
Pins P80/SEG25
Other Functions Segment output (SEG25) None (LVD reference voltage external input pin)*3 10-bit PWM output None Common output (COM4 to COM1) A/D converter analog input External interrupt 1 A/D converter analog input A/D converter analog input (LVD detection voltage external input pin)*5
P95 to P92 (P95, P92, High-voltage, large-current P93/Vref)*3 2 port* P91, P90/ PWM2, PWM1 High-voltage, input port*4 4-bit I/O port IRQAEC PA3 to PA0/ COM4 to COM1 PB3/AN3/
1QRI
* Port A *
LPCR
Port B
*
4-bit input-only port
AMR PMRB AMR AMR (LVDCR)*5
PB2/AN2 PB1/AN1/ (extU)*5 PB0/AN0/ (extD)*5
Notes: 1. Implemented on H8/3802 Group and H8/38104 Group only. 2. Implemented on H8/3802 Group only. Standard high-voltage port on H8/38104 Group, H8/38002S Group and H8/38004 Group. 3. Implemented on H8/38104 Group only. Pin 94 does not function on H8/38104 Group. 4. Implemented on H8/3802 Group only. Input port on H8/38004 Group, H8/38002S Group and H8/38104 Group. 5. Implemented on H8/38104 Group only.
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Section 8 I/O Ports
8.1
Port 3
Port 3 is an I/O port also functioning as an asynchronous event counter input pin and timer F output pin. Figure 8.1 shows its pin configuration.
P37/AEVL P36/AEVH P35 Port 3 P34 P33 P32/TMOFH
P31/TMOFL
Figure 8.1 Port 3 Pin Configuration Port 3 has the following registers. * * * * * Port data register 3 (PDR3) Port control register 3 (PCR3) Port pull-up control register 3 (PUCR3) Port mode register 3 (PMR3) Port mode register 2 (PMR2)
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Section 8 I/O Ports
8.1.1
Port Data Register 3 (PDR3)
PDR3 is a register that stores data of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37 P36 P35 P34 P33 P32 P31 Initial Value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Reserved Description If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
8.1.2
Port Control Register 3 (PCR3)
PCR3 controls whether each of the port 3 pins functions as an input pin or output pin.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W W Reserved The write value should always be 0. Description Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. PCR3 is a write-only register. Bits 7 to 1 are always read as 1.
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Section 8 I/O Ports
8.1.3
Port Pull-Up Control Register 3 (PUCR3)
PUCR3 controls whether the pull-up MOS of each of the port 3 pins is on or off.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 Initial Value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W W Reserved The write value should always be 0. Description When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
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Section 8 I/O Ports
8.1.4
Port Mode Register 3 (PMR3)
PMR3 controls the selection of pin functions for port 3 pins.
Bit 7 Bit Name AEVL Initial Value 0 R/W R/W Description P37/AEVL Pin Function Switch This bit selects whether pin P37/AEVL is used as P37 or as AEVL. 0: P37 I/O pin 1: AEVL input pin 6 AEVH 0 R/W P36/AEVH Pin Function Switch This bit selects whether pin P36/AEVH is used as P36 or as AEVH. 0: P36 I/O pin 1: AEVH input pin 5 to 3 2 TMOFH 0 W R/W Reserved The write value should always be 0. P32/TMOFH Pin Function Switch This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH. 0: P32 I/O pin 1: TMOFH output pin 1 TMOFL 0 R/W P31/TMOFL Pin Function Switch This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL. 0: P31 I/O pin 1: TMOFL output pin 0 W Reserved The write value should always be 0.
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Section 8 I/O Ports
8.1.5
Port Mode Register 2 (PMR2)
PMR2 controls the PMOS on/off state for the P35 pin, selects a pin function for the P43/IRQ0 pin, and selects a clock of the watchdog timer.
Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 POF1 0 R/W P35 Pin PMOS Control This bit controls the on/off state of the PMOS of the P35 pin output buffer. 0: CMOS output 1: NMOS open-drain output 4, 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 WDCKS 0 R/W Watchdog Timer Source Clock Select This bit selects the input clock for the watchdog timer. Note that this bit is implemented differently on the H8/38004, H8/38002S Group and on H8/38104 Group. H8/38004, H8/38002S Group: 0: /8,192 1: w/32 H8/38104 Group: 0: Clock specified by timer mode register W (TMW) 1: w/32 Note: This bit is reserved and only 0 can be written in the H8/3802 Group. 1 0 IRQ0 0 W R/W Reserved The write value should always be 0. P43/IRQ0 Pin Function Switch This bit selects whether pin P43/IRQ0 is used as P43 or as . 0: P43 input pin
0QRI 0QRI
1:
input pin
Note: * See section 9.5, Watchdog Timer, for details.
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Section 8 I/O Ports
8.1.6
Pin Functions
The port 3 pin functions are shown below. * P37/AEVL pin The pin function depends on the combination of bit AEVL in PMR3 and bit PCR37 in PCR3.
AEVL PCR37 Pin Function Legend: *: Don't care. 0 P37 input pin 0 1 P37 output pin 1 * AEVL input pin
* P36/AEVH pin The pin function depends on the combination of bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH PCR36 Pin Function Legend: *: Don't care. 0 P36 input pin 0 1 P36 output pin 1 * AEVH input pin
* P35 to P33 pins The pin function depends on the corresponding bit in PCR3.
(n = 5 to 3) PCR3n Pin Function 0 P3n input pin 1 P3n output pin
* P32/TMOFH pin The pin function depends on the combination of bit TMOFH in PMR3 and bit PCR32 in PCR3.
TMOFH PCR32 Pin Function Legend: *: Don't care. 0 P32 input pin 0 1 P32 output pin 1 * TMOFH output pin
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Section 8 I/O Ports
* P31/TMOFL pin The pin function depends on the combination of bit TMOFL in PMR3 and bit PCR31 in PCR3.
TMOFL PCR31 Pin Function Legend: *: Don't care. 0 P31 input pin 0 1 P31 output pin 1 * TMOFL output pin
8.1.7
Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 1) PCR3n PUCR3n Input Pull-Up MOS Legend: *: Don't care. 0 Off 0 1 On 1 * Off
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Section 8 I/O Ports
8.2
Port 4
Port 4 is an I/O port also functioning as an interrupt input pin and SCI I/O pin. Figure 8.2 shows its pin configuration.
P43/ P42/TXD32 Port 4 P41/RXD32 P40/SCK32
Figure 8.2 Port 4 Pin Configuration Port 4 has the following registers. * Port data register 4 (PDR4) * Port control register 4 (PCR4) * Serial port control register (SPCR) 8.2.1 Port Data Register 4 (PDR4)
PDR4 is a register that stores data of port 4.
Bit 7 to 4 3 2 1 0 Bit Name P43 P42 P41 P40 Initial Value 1 1 0 0 0 R/W R R/W R/W R/W Description Reserved These bits are always read as 1. If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read.
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Section 8 I/O Ports
8.2.2
Port Control Register 4 (PCR4)
PCR4 controls whether each of the port 4 pins functions as an input pin or output pin.
Bit 7 to 3 2 1 0 Bit Name PCR42 PCR41 PCR40 Initial Value All 1 0 0 0 R/W W W W Description Reserved These bits are always read as 1. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR4 and in PDR4 are valid only when the corresponding pin is designated in SCR3 and SCR2 as a general I/O pin. PCR4 is a write-only register. Bits 2 to 0 are always read as 1.
8.2.3
Serial Port Control Register (SPCR)
SPCR performs input/output data inversion switching of the RXD32 and TXD32 pins. Figure 8.3 shows the configuration.
SCINV2 RXD32
P41/RXD32
SCINV3 P42/TXD32
TXD32
Figure 8.3 Input/Output Data Inversion Function
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Section 8 I/O Ports Initial Value All 1 0
Bit 7, 6 5
Bit Name SPC32
R/W R/W
Description Reserved These bits are always read as 1 and cannot be modified. P42/TXD32 Pin Function Switch This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. 0: P42 I/O pin 1: TXD32 output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1.
4 3
SCINV3
0
W R/W
Reserved The write value should always be 0. TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 pin output data is inverted. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted
2
SCINV2
0
R/W
RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 pin input data is inverted. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted
1, 0
W
Reserved The write value should always be 0.
Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
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Section 8 I/O Ports
8.2.4
Pin Functions
The port 4 pin functions are shown below. * P43/IRQ0 pin The pin function depends on the IRQ0 bit in PMR2.
IRQ0 Pin Function 0
0QRI
1 input pin
P43 input pin
* P42/TXD32 pin The pin function depends on the combination of bit TE in SCR3, bit SPC32 in SPCR, and bit PCR42 in PCR4.
SPC32 TE PCR42 Pin Function Legend: *: Don't care. 0 P42 input pin 0 0 1 P42 output pin 1 1 * TXD32 output pin
* P41/RXD32 pin The pin function depends on the combination of bit RE in SCR3 and bit PCR41 in PCR4.
RE PCR41 Pin Function Legend: *: Don't care. 0 P41 input pin 0 1 P41 output pin 1 * RXD32 input pin
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Section 8 I/O Ports
* P40/SCK32 pin The pin function depends on the combination of bits CKE1 and CKE0 in SCR3, bit COM in SMR, and bit PCR40 in PCR4.
CKE1 CKE0 COM PCR40 Pin Function Legend: *: Don't care. 0 P40 input pin 0 1 P40 output pin 0 1 * SCK32 output pin 0 1 * 1 * * * SCK32 input pin
8.3
Port 5
Port 5 is an I/O port also functioning as a wakeup interrupt request input pin and LCD segment output pin. Figure 8.4 shows its pin configuration.
P57/ P56/ P55/ Port 5 P54/ P53/ P52/ P51/ P50/
/SEG8 /SEG7 /SEG6 /SEG5 /SEG4 /SEG3 /SEG2 /SEG1
Figure 8.4 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port data register 5 (PDR5) Port control register 5 (PCR5) Port pull-up control register 5 (PUCR5) Port mode register 5 (PMR5)
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Section 8 I/O Ports
8.3.1
Port Data Register 5 (PDR5)
PDR5 is a register that stores data of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
8.3.2
Port Control Register 5 (PCR5)
PCR5 controls whether each of the port 5 pins functions as an input pin or output pin.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid only when the corresponding pin is designated by PMR5 and the SGS3 to SGS0 bits in LPCR as a general I/O pin. PCR5 is a write-only register. Bits 7 to 0 are always read as 1.
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Section 8 I/O Ports
8.3.3
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls whether the pull-up MOS of each of the port 5 pins is on or off.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
8.3.4
Port Mode Register 5 (PMR5)
PMR5 controls the selection of pin functions for port 5 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P5n/WKPn/SEGn+1 Pin Function Switch When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as P5n or .
nPKW
0: P5n I/O pin (n = 7 to 0)
nPKW
1:
input pin
Note: For use as SEGn+1, see section 13.3.1, LCD Port Control Register (LPCR).
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Section 8 I/O Ports
8.3.5
Pin Functions
The port 5 pin functions are shown below. * P57/WKP7/SEG8 to P54/WKP4/SEG5 pins The pin function depends on the combination of bit WKPn in PMR5, bit PCR5n in PCR5, and bits SGS3 to SGS0 in LPCR.
(n = 7 to 4) SGS3 to SGS0 WKPn PCR5n 0 Other than B0010, B0011, B0100, B0101, B0110, B0111, B1000, B1001 0 1 P5n output pin 1 * WKPn input pin B0010, B0011, B0100, B0101, B0110, B0111, B1000, B1001 * * SEGn+1 output pin
Pin Function P5n input pin Legend: *: Don't care.
* P53/WKP3/SEG4 to P50/WKP0/SEG1 pins The pin function depends on the combination of bit WKPm in PMR5, bit PCR5m in PCR5, and bits SGS3 to SGS0 in LPCR.
(m = 3 to 0) SGS3 to SGS0 WKPm PCR5m 0 Other than B0001, B0010, B0011, B0100, B0101, B0110, B0111, B1000 0 1 1 * B0001, B0010, B0011, B0100, B0101, B0110, B0111, B1000 * * SEGm+1 output pin
Pin Function P5m input pin P5m output pin WKPm input pin Legend: *: Don't care.
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Section 8 I/O Ports
8.3.6
Input Pull-Up MOS
Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0) PCR5n PUCR5n Input Pull-Up MOS Legend: *: Don't care. 0 Off 0 1 On 1 * Off
8.4
Port 6
Port 6 is an I/O port also functioning as an LCD segment output pin. Figure 8.5 shows its pin configuration.
P67/SEG16 P66/SEG15 P65/SEG14 Port 6 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9
Figure 8.5 Port 6 Pin Configuration Port 6 has the following registers. * Port data register 6 (PDR6) * Port control register 6 (PCR6) * Port pull-up control register 6 (PUCR6)
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Section 8 I/O Ports
8.4.1
Port Data Register 6 (PDR6)
PDR6 is a register that stores data of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
8.4.2
Port Control Register 6 (PCR6)
PCR6 controls whether each of the port 6 pins functions as an input pin or output pin.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR6 and in PDR6 are valid only when the corresponding pin is designated by the SGS3 to SGS0 bits in LPCR as a general I/O pin. PCR6 is a write-only register. Bits 7 to 0 are always read as 1.
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Section 8 I/O Ports
8.4.3
Port Pull-Up Control Register 6 (PUCR6)
PUCR6 controls whether the pull-up MOS of each of the port 6 pins is on or off.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
8.4.4
Pin Functions
The port 6 pin functions are shown below. * P67/SEG16 to P64/SEG13 pins The pin function depends on the combination of bit PCR6n in PCR6 and bits SGS3 to SGS0 in LPCR.
(n = 7 to 4) SGS3 to SGS0 PCR6n Pin Function Legend: *: Don't care. Other than B0100, B0101, B0110, B0111, B1000, B1001, B1010, B1011 0 P6n input pin 1 P6n output pin B0100, B0101, B0110, B0111, B1000, B1001, B1010, B1011 * SEGn+9 output pin
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Section 8 I/O Ports
* P63/SEG12 to P60/SEG9 pins The pin function depends on the combination of bit PCR6m in PCR6 and bits SGS3 to SGS0 in LPCR.
(m = 3 to 0) SGS3 to SGS0 PCR6m Pin Function Legend: *: Don't care. Other than B0011, B0100, B0101, B0110, B0111, B1000, B1001, B1010 0 P6m input pin 1 P6m output pin B0011, B0100, B0101, B0110, B0111, B1000, B1001, B1010 * SEGm+9 output pin
8.4.5
Input Pull-Up MOS
Port 6 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0) PCR6n PUCR6n Input Pull-Up MOS Legend: *: Don't care. 0 Off 0 1 On 1 * Off
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Section 8 I/O Ports
8.5
Port 7
Port 7 is an I/O port also functioning as an LCD segment output pin. Figure 8.6 shows its pin configuration.
P77/SEG24 P76/SEG23 P75/SEG22 Port 7 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17
Figure 8.6 Port 7 Pin Configuration Port 7 has the following registers. * Port data register 7 (PDR7) * Port control register 7 (PCR7) 8.5.1 Port Data Register 7 (PDR7)
PDR7 is a register that stores data of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name P77 P76 P75 P74 P73 P72 P71 P70 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
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Section 8 I/O Ports
8.5.2
Port Control Register 7 (PCR7)
PCR7 controls whether each of the port 7 pins functions as an input pin or output pin.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid only when the corresponding pin is designated by the SGS3 to SGS0 bits in LPCR as a general I/O pin. PCR7 is a write-only register. Bits 7 to 0 are always read as 1.
8.5.3
Pin Functions
The port 7 pin functions are shown below. * P77/SEG24 to P74/SEG21 pins The pin function depends on the combination of bit PCR7n in PCR7 and bits SGS3 to SGS0 in LPCR.
(n = 7 to 4) SGS3 to SGS0 PCR7n Pin Function Legend: *: Don't care. Other than B'0110, B'0111, B'1000, B'1001, B'1010, B'1011, B'1100, B'1101 0 P7n input pin 1 P7n output pin B'0110, B'0111, B'1000, B'1001, B'1010, B'1011, B'1100, B'1101 * SEGn+17 output pin
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Section 8 I/O Ports
* P73/SEG20 to P70/SEG17 pins The pin function depends on the combination of bit PCR7m in PCR7 and bits SGS3 to SGS0 in LPCR.
(m = 3 to 0) SGS3 to SGS0 PCR7m Pin Function Legend: *: Don't care. Other than B'0101, B'0110, B'0111, B'1000, B'1001, B'1010, B'1011, B'1100 0 P7m input pin 1 P7m output pin B'0101, B'0110, B'0111, B'1000, B'1001, B'1010, B'1011, B'1100 * SEGm+17 output pin
8.6
Port 8
Port 8 is an I/O port also functioning as an LCD segment output pin. Figure 8.7 shows its pin configuration.
Port 8
P80/SEG25
Figure 8.7 Port 8 Pin Configuration Port 8 has the following registers. * Port data register 8 (PDR8) * Port control register 8 (PCR8)
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Section 8 I/O Ports
8.6.1
Port Data Register 8 (PDR8)
PDR8 is a register that stores data of port 8.
Bit 7 to 1 0 Bit Name P80 Initial Value 0 R/W R/W Description Reserved If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
8.6.2
Port Control Register 8 (PCR8)
PCR8 controls whether each of the port 8 pins functions as an input pin or output pin.
Bit 7 to 1 0 Bit Name PCR80 Initial Value 0 R/W W W Description Reserved The write value should always be 0. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR8 and in PDR8 are valid only when the corresponding pin is designated by the SGS3 to SGS0 bits in LPCR as a general I/O pin. PCR8 is a write-only register.
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Section 8 I/O Ports
8.6.3
Pin Functions
The port 8 pin functions are shown below. * P80/SEG25 pin The pin function depends on the combination of bit PCR80 in PCR8 and bits SGS3 to SGS0 in LPCR.
SGS3 to SGS0 PCR80 Pin Function Legend: *: Don't care. Other than B'0111, B'1000, B'1001, B'1010, B'1011, B'1100, B'1101, B'1110 0 P80 input pin 1 P80 output pin B'0111, B'1000, B'1001, B'1010, B'1011, B'1100, B'1101, B'1110 * SEG25 output pin
8.7
Port 9
Port 9 is a dedicated current port for NMOS output that also functions as a PWM output pin. Figure 8.8 shows its pin configuration.
P95 P94*1 P93/Vref*2 Port 9 P92 P91/PWM2 P90/PWM1
Notes: 1. There is no pin 94, and its function is not implemented, on the H8/38104 Group. 2. The Vref pin is implemented on the H8/38104 Group only.
Figure 8.8 Port 9 Pin Configuration Port 9 has the following registers. * Port data register 9 (PDR9) * Port mode register 9 (PMR9)
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Section 8 I/O Ports
8.7.1
Port Data Register 9 (PDR9)
PDR9 is a register that stores data of port 9.
Bit 7, 6 5 4 3 2 1 0 Bit Name P95 P94* P93 P92 P91 P90 Initial Value All 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. If PDR9 is read, the values stored in PDR9 are read.
Note: * There is no pin 94, and its function is not implemented, on the H8/38104 Group. However, the register is read/write enabled.
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Section 8 I/O Ports
8.7.2
Port Mode Register 9 (PMR9)
PMR9 controls the selection of the P90 and P91 pin functions.
Bit 7 to 4 3 Bit Name PIOFF Initial Value All 1 0 R/W R/W Description Reserved The initial value should not be changed. P92 to P90 Step-Up Circuit Control This bit turns on and off the P92 to P90 step-up circuit. 0: Step-up circuit of large-current port is turned on 1: Step-up circuit of large-current port is turned off Note: This bit is valid in the H8/3802 Group only. It functions as a readable/writable reserved bit in versions other than the H8/3802 Group. 2 1 0 PWM2 PWM1 0 0 W R/W R/W Reserved The write value should always be 0. P9n/PWMn+1 Pin Function Switch These bits select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. (n = 1, 0) 0: P9n output pin 1: PWMn+1 output pin Note: When turning the step-up circuit on or off, the register must be rewritten only when the buffer NMOS is off (port data is 1). When turning the step-up circuit on, first clear PIOFF to 0, then wait for the elapse of 30 system clock before turning the buffer NMOS on (clearing port data to 0). Without the elapse of the 30 system clock interval the step-up circuit will not start up, and it will not be possible for a large current to flow, making operation unstable.
8.7.3
Pin Functions
The port 9 pin functions are shown below. * P91/PWMn+1 to P90/PWMn+1 pins
(n = 1, 0) PMR9n Pin Function 0 P9n output pin 1 PWMn+1 output pin
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Section 8 I/O Ports
* P93/Vref As shown below, switching is performed based on the setting of VREFSEL in LVDSR. Note that this function is implemented on the H8/38104 Group only. The Vref pin is the input pin for the LVD's external reference voltage.
VREFSEL Pin Function 0 P93 output pin 1 Vref input pin
8.8
Port A
Port A is an I/O port also functioning as an LCD common output pin. Figure 8.9 shows its pin configuration.
PA3/COM4 Port A PA2/COM3 PA1/COM2 PA0/COM1
Figure 8.9 Port A Pin Configuration Port A has the following registers. * Port data register A (PDRA) * Port control register A (PCRA)
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Section 8 I/O Ports
8.8.1
Port Data Register A (PDRA)
PDRA is a register that stores data of port A.
Bit 7 to 4 3 2 1 0 Bit Name PA3 PA2 PA1 PA0 Initial Value All 1 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read.
8.8.2
Port Control Register A (PCRA)
PCRA controls whether each of the port A pins functions as an input pin or output pin.
Bit 7 to 4 3 2 1 0 Bit Name PCRA3 PCRA2 PCRA1 PCRA0 Initial Value All 1 0 0 0 0 R/W W W W W Description Reserved The initial value should not be changed. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRA and in PDRA are valid only when the corresponding pin is designated in LPCR as a general I/O pin. PCRA is a write-only register. Bits 3 to 0 are always read as 1.
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Section 8 I/O Ports
8.8.3
Pin Functions
The port A pin functions are shown below. * PA3/COM4 pin The pin function depends on the combination of bit PCRA3 in PCRA and bits SGS3 to SGS0 in LPCR.
SGS3 to SGS0 PCRA3 Pin Function Legend: *: Don't care. B'0000 0 PA3 input pin B'0000 1 PA3 output pin Other than B'0000 * COM4 output pin
* PA2/COM3 pin The pin function depends on the combination of bit PCRA2 in PCRA and bits SGS3 to SGS0 in LPCR.
SGS3 to SGS0 PCRA2 Pin Function Legend: *: Don't care. B'0000 0 PA2 input pin B'0000 1 PA2 output pin Other than B'0000 * COM3 output pin
* PA1/COM2 pin The pin function depends on the combination of bit PCRA1 in PCRA and bits SGS3 to SGS0 in LPCR.
SGS3 to SGS0 PCRA1 Pin Function Legend: *: Don't care. B'0000 0 PA1 input pin B'0000 1 PA1 output pin Other than B'0000 * COM2 output pin
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Section 8 I/O Ports
* PA0/COM1 pin The pin function depends on the combination of bit PCRA0 in PCRA and bits SGS3 to SGS0 in LPCR.
SGS3 to SGS0 PCRA0 Pin Function Legend: *: Don't care. B'0000 0 PA0 input pin B'0000 1 PA0 output pin Other than B'0000 * COM1 output pin
8.9
Port B
Port B is an input-only port also functioning as an analog input pin and interrupt input pin. Figure 8.10 shows its pin configuration.
PB3/AN3/143 Port B PB2/AN2 PB1/AN1/extU* PB0/AN0/extD*
Note: * The extU and extD pins are implemented on the H8/38104 Group only.
Figure 8.10 Port B Pin Configuration Port B has the following registers. * Port data register B (PDRB) * Port mode register B (PMRB)
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Section 8 I/O Ports
8.9.1
Port Data Register B (PDRB)
PDRB is a register that stores data of port B.
Bit 7 to 4 3 2 1 0 Bit Name PB3 PB2 PB1 PB0 Initial Value R/W Description Reserved Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by bits CH3 to CH0 in AMR, that pin reads 0 regardless of the input voltage.
Undefined Undefined R R R R
8.9.2
Port Mode Register B (PMRB)
PMRB controls the selection of the PB3 pin functions.
Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 IRQ1 0 R/W PB3/AN3/IRQ1 Pin Function Switch This bit selects whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as . 0: PB3/AN3 input pin 2 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified.
1QRI 1QRI
1:
input pin
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Section 8 I/O Ports
8.9.3
Pin Functions
The port B pin functions are shown below. * PB3/AN3/IRQ1 pin The pin function depends on the combination of bits CH3 to CH0 in AMR and bit IRQ1 in PMRB.
IRQ1 CH3 to CH0 Pin Function Other than B'0111 PB3 input pin 0 B'0111
1QRI
1 * input pin
AN3 input pin
Legend: *: Don't care.
* PB2/AN2 pin The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0 Pin Function Other than B'0110 PB2 input pin B'0110 AN2 input pin
* PB1/AN1/extU pin Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in LVDCR as shown below. Note that the extU pin and VINTUSEL are implemented on the H8/38104 Group only.
VINTUSEL CH3 to CH0 Pin Function Legend: *: Don't care Other than B'0101 PB1 input pin 0 B'0101 AN1 input pin 1 * extU input pin
* PB0/AN0/extD pin Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in LVDCR as shown below. Note that the extD pin and VINTDSEL are implemented on the H8/38104 Group only.
VINTDSEL CH3 to CH0 Pin Function Legend: *: Don't care Other than B'0100 PB0 input pin 0 B'0100 AN0 input pin 1 * extD input pin
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Section 8 I/O Ports
8.10
8.10.1
Usage Notes
How to Handle Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down. * If an unused pin is an input pin, handle it in one of the following ways: Pull it up to Vcc with an on-chip pull-up MOS. Pull it up to Vcc with an external resistor of approximately 100 k. Pull it down to Vss with an external resistor of approximately 100 k. For a pin also used by the A/D converter, pull it up to AVcc. * If an unused pin is an output pin, handle it in one of the following ways: Set the output of the unused pin to high and pull it up to Vcc with an on-chip pull-up MOS. Set the output of the unused pin to high and pull it up to Vcc with an external resistor of approximately 100 k. Set the output of the unused pin to low and pull it down to GND with an external resistor of approximately 100 k.
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Section 8 I/O Ports
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Section 9 Timers
Section 9 Timers
9.1 Overview
The H8/3802 Group provides three timers: timer A, timer F, and asynchronous event counter. The H8/38004 Group, H8/38002S Group and H8/38104 Group provide four timers: timer A, timer F, asynchronous event counter, and watchdog timer. The functions of these timers are summarized in table 9.1.
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Section 9 Timers
Table 9.1
Name Timer A
Timer Functions
Functions * * * 8-bit timer Interval function Clock time base Internal Clock /8 to /8192 (8 choices) W /128 (choice of 4 overflow periods) /4 to /32, W /4 -- (4 choices) TMOFL TMOFH Event Input Waveform Pin Output Pin -- -- Remarks
Timer F
* *
16-bit timer Also usable as two independent 8-bit timers. Output compare output function 16-bit counter Also usable as two independent 8-bit counters Counts events asynchronous to and W Can count asynchronous events (rising/falling/both edges) independently of the MCU's internal clock
* Asynchronous event counter * *
/2 to /8 (3 choices)
AEVL AEVH IRQAEC
--
*
*
Watchdog timer*
*
/8192, W /32 Generates a reset signal by overflow of 8-bit counter /64 to /8192 w/32 On-chip oscillator
H8/38004, H8/38002S Group H8/38104 Group
Note: * The watchdog timer functions differently on the H8/38004, H8/38002S and H8/38104 Group. See section 9.5, Watchdog Timer, for details.
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Section 9 Timers
9.2
Timer A
The timer A is an 8-bit timer with interval timing and realtime clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 9.1 shows a block diagram of the timer A. 9.2.1 Features
* The timer A can be used as an interval timer or a clock time base. * An interrupt is requested when the counter overflows. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) Interval Timer * Choice of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, and 8) Clock Time Base * Choice of four overflow periods (1 s, 0.5 s, 0.25 s, and 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator).
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Section 9 Timers
W
1/4
W/4
PSW
TMA
W/128
TCA
/8192, /4096, /2048, /512, /256, /128, /32, /8
/128*
PSS
/256*
/64*
/8*
IRRTA
Legend: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (W/128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A 9.2.2 Register Descriptions
The timer A has the following registers. * Timer mode register A (TMA) * Timer counter A (TCA) Timer Mode Register A (TMA): TMA selects the operating mode, the divided clock output, and the input clock.
Bit 7 6 5 Bit Name Initial Value R/W W W W Description Reserved The write value should always be 0.
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Internal data bus
Section 9 Timers Initial Value 1 0
Bit 4 3
Bit Name TMA3
R/W R/W
Description Reserved This bit is always read as 1. Internal Clock Select 3 Selects the operating mode of the timer A. 0: Functions as an interval timer to count the outputs of prescaler S. 1: Functions as a clock-time base to count the outputs of prescaler W.
2 1 0
TMA2 TMA1 TMA0
0 0 0
R/W R/W R/W
Internal Clock Select 2 to 0 Select the clock input to TCA when TMA3 = 0. 000: /8192 001: /4096 010: /2048 011: /512 100: /256 101: /128 110: /32 111: /8 These bits select the overflow period when TMA3 = 1 (when a 32.768 kHz crystal oscillator is used as w). 000: 1 s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1XX: Both PSW and TCA are reset
Legend: X: Don't care.
Timer Counter A (TCA): TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in TMA. TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in the interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 in TMA to B'11. TCA is initialized to H'00.
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Section 9 Timers
9.2.3
Operation
Interval Timer Operation: When bit TMA3 in TMA is cleared to 0, the timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of the timer A resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in the interrupt enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and starts counting up again. In this mode the timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Clock Time Base Operation: When bit TMA3 in TMA is set to 1, the timer A functions as a clock-timer base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00. 9.2.4 Timer A Operating States
Table 9.2 summarizes the timer A operating states. Table 9.2 Timer A Operating States
Reset Reset Active Functions Functions* Functions Sleep Functions Functions* Retained Watch Halted Functions Retained Sub-active Sub-sleep Halted Functions Functions Halted Functions Retained Standby Halted Halted Retained Module Standby Halted Halted Retained
Operating Mode TCA Interval
Clock Reset time base TMA Reset
Note:
*
When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in the count cycle.
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Section 9 Timers
9.3
Timer F
The timer F has a 16-bit timer having an output compare function. The timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Thus, it can be applied to various systems. The timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Figure 9.2 shows a block diagram of the timer F. 9.3.1 Features
* Choice of four internal clock sources (/32, /16, /4, and W/4) * Toggle output function Toggle output is performed to the TMOFH pin (TMOFL pin) using a single compare match signal. The initial value of toggle output can be set. * Counter resetting by a compare match signal * Two interrupt sources: One compare match, one overflow * Choice of 16-bit or 8-bit mode by settings of bits CKSH2 to CKSH0 in TCRF * Can operate in watch mode, subactive mode, and subsleep mode When W/4 is selected as an internal clock, the timer F can operate in watch mode, subactive mode, and subsleep mode. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.)
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Section 9 Timers
PSS
IRRTFL
TCRF
W/4 Toggle circuit
TCFL
TMOFL
Comparator
OCRFL
TCFH Toggle circuit
TMOFH
Comparator
Match
OCRFH
TCSRF Legend: TCRF: TCFH: TCFL: Timer control register F 8-bit timer counter FH 8-bit timer counter FL TCSRF: Timer control status register F IRRTFH
OCRFH: Output compare register FH OCRFL: Output compare register FL IRRTFH: Timer FH interrupt request flag IRRTFL: Timer FL interrupt request flag PSS: Prescaler S
Figure 9.2 Block Diagram of Timer F
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Internal data bus
Section 9 Timers
9.3.2
Input/Output Pins
Table 9.3 shows the pin configuration of the timer F. Table 9.3
Name Timer FH output Timer FL output
Pin Configuration
Abbreviation I/O TMOFH TMOFL Output Output Function Timer FH toggle output pin Timer FL toggle output pin
9.3.3
Register Descriptions
The timer F has the following registers. * * * * Timer counters FH and FL (TCFH,TCFL) Output compare registers FH and FL (OCRFH, OCRFL) Timer control register F (TCRF) Timer control status register F (TCSRF)
Timer Counters FH and FL (TCFH, TCFL): TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see section 9.3.4, CPU Interface. TCFH and TCFL are initialized to H'00 upon reset. * 16-bit mode (TCF) When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF. TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is sent to the CPU. * 8-bit mode (TCFL/TCFH) When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in TCRF.
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Section 9 Timers
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU. Output Compare Registers FH and FL (OCRFH, OCRFL): OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see section 9.3.4, CPU Interface. OCRFH and OCRFL are initialized to H'FF upon reset. * 16-bit mode (OCRF) When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin by means of compare matches, and the output level can be set (high or low) by means of TOLH in TCRF. * 8-bit mode (OCRFH/OCRFL) When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
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Section 9 Timers
Timer Control Register F (TCRF): TCRF switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources, and sets the output level of the TMOFH and TMOFL pins.
Bit 7 Bit Name TOLH Initial Value 0 R/W W Description Toggle Output Level H Sets the TMOFH pin output level. 0: Low level 1: High level Clock Select H Select the clock input to TCFH from among four internal clock sources or TCFL overflow. 000: 16-bit mode, counting on TCFL overflow signal 001: 16-bit mode, counting on TCFL overflow signal 010: 16-bit mode, counting on TCFL overflow signal 011: Using prohibited 100: Internal clock: counting on /32 101: Internal clock: counting on /16 110: Internal clock: counting on /4 111: Internal clock: counting on W /4 Toggle Output Level L Sets the TMOFL pin output level. 0: Low level 1: High level 2 1 0 CKSL2 CKSL1 CKSL0 0 0 0 W W W Clock Select L Select the clock input to TCFL from among four internal clock sources or external event input. 000: Non-operational 001: Using prohibited 010: Using prohibited 011: Using prohibited 100: Internal clock: counting on /32 101: Internal clock: counting on /16 110: Internal clock: counting on /4 111: Internal clock: counting on W /4
6 5 4
CKSH2 CKSH1 CKSH0
0 0 0
W W W
3
TOLL
0
W
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Section 9 Timers
Timer Control Status Register F (TCSRF): TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Bit 7 Bit Name OVFH Initial Value 0 R/W R/W * Description Timer Overflow Flag H [Setting condition] When TCFH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVFH = 1 6 CMFH 0 R/W * Compare Match Flag H This is a status flag indicating that TCFH has matched OCRFH. [Setting condition] When the TCFH value matches the OCRFH value [Clearing condition] When this bit is written to 0 after reading CMFH = 1 5 OVIEH 0 R/W Timer Overflow Interrupt Enable H Selects enabling or disabling of interrupt generation when TCFH overflows. 0: TCFH overflow interrupt request is disabled 1: TCFH overflow interrupt request is enabled 4 CCLRH 0 R/W Counter Clear H In 16-bit mode, this bit selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, this bit selects whether TCFH is cleared when TCFH and OCRFH match. In 16-bit mode: 0: TCF clearing by compare match is disabled 1: TCF clearing by compare match is enabled In 8-bit mode: 0: TCFH clearing by compare match is disabled 1: TCFH clearing by compare match is enabled
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Section 9 Timers Initial Value 0
Bit 3
Bit Name OVFL
R/W R/W *
Description Timer Overflow Flag L This is a status flag indicating that TCFL has overflowed. [Setting condition] When TCFL overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVFL = 1
2
CMFL
0
R/W *
Compare Match Flag L This is a status flag indicating that TCFL has matched OCRFL. [Setting condition] When the TCFL value matches the OCRFL value [Clearing condition] When this bit is written to 0 after reading CMFL = 1
1
OVIEL
0
R/W
Timer Overflow Interrupt Enable L Selects enabling or disabling of interrupt generation when TCFL overflows. 0: TCFL overflow interrupt request is disabled 1: TCFL overflow interrupt request is enabled
0
CCLRL
0
R/W
Counter Clear L Selects whether TCFL is cleared when TCFL and OCRFL match. 0: TCFL clearing by compare match is disabled 1: TCFL clearing by compare match is enabled
Note:
*
Only 0 can be written to clear the flag.
9.3.4
CPU Interface
TCF and OCRF are 16-bit readable/writable registers, but the CPU is connected to the on-chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be transferred correctly if only the upper byte or only the lower byte is accessed. Access must be performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte.
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In 8-bit mode, there are no restrictions on the order of access. Write Access: Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9.3 shows an example in which H'AA55 is written to TCF.
Write to upper byte Module data bus CPU [H'AA] Bus interface
TEMP [H'AA]
TCFH [ ]
TCFL [ ]
Write to lower byte Module data bus CPU [H'55] Bus interface
TEMP [H'AA]
TCFH [H'AA]
TCFL [H'55]
Figure 9.3 Write Access to TCF (CPU TCF) Read Access: In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU. Figure 9.4 shows an example in which TCF is read when it contains H'AAFF.
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Section 9 Timers
Read upper byte Module data bus
CPU [H'AA]
Bus interface
TEMP [H'FF]
TCFH [H'AA]
TCFL [H'FF]
Read lower byte Module data bus CPU [H'FF] Bus interface
TEMP [H'FF]
TCFH [AB] * Note: H'AB00 if counter has been updated once.
TCFL [00] *
Figure 9.4 Read Access to TCF (TCF CPU) 9.3.5 Operation
The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in the output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. The timer F can also function as two independent 8-bit timers. Timer F Operation: The timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below.
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* Operation in 16-bit timer mode When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit timer. The timer F operating clock can be selected from three internal clocks output by prescaler S by means of bits CKSL2 to CKSL0 in TCRF. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. TMOFH pin output can also be set by TOLH in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU. * Operation in 8-bit timer mode When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in TCRF. When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU. TCF Increment Timing: TCF is incremented by clock input (internal clock input). Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (/32, /16, /4, or W/4) created by dividing the system clock ( or W). TMOFH/TMOFL Output Timing: In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 9.5 shows the output timing.
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Section 9 Timers
Count input clock
TCF
N
N+1
N
N+1
OCRF
N
N
Compare match signal
TMOFH, TMOFL
Figure 9.5 TMOFH/TMOFL Output Timing TCF Clear Timing: TCF can be cleared by a compare match with OCRF. Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Compare Match Flag Set Timing: The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock.
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Section 9 Timers
9.3.6
Timer F Operating States
The timer F operating states are shown in table 9.4. Table 9.4
Operating Mode
TCF
Timer F Operating States
Reset
Reset
Active
Functions*
Sleep
Functions*
Watch
Functions/ Halted* Retained Retained Retained
Sub-active Sub-sleep Standby
Functions/ Halted* Functions Functions Functions Functions/ Halted* Retained Retained Retained Halted
Module Standby
Halted
OCRF TCRF TCSRF
Reset Reset Reset
Functions Functions Functions
Retained Retained Retained
Retained Retained Retained
Retained Retained Retained
Note:
*
When W /4 is selected as the TCF internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, W /4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected.
9.3.7
Usage Notes
The following types of contention and operation can occur when the timer F is used. 16-Bit Timer Mode: In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be used as a port pin. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated. Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
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Section 9 Timers
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 8-Bit Timer Mode: * TCFH, OCRFH In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. If an OCRFH write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not output. * TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer Overflow Flags H, L (OVFH, OVFL), and Compare Match Flags H, L (CMFH, CMFL): When W/4 is selected as the internal clock, "Interrupt source generation signal" will be operated with W and the signal will be outputted with W width. And, "Overflow signal" and "Compare match signal" are controlled with 2 cycles of W signals. Those signals are outputted with 2 cycles width of W (figure 9.6) In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of "Interrupt source generation signal", same interrupt request flag is set. (1 in figure 9.6) And, the timer overflow flag and compare match flag cannot be cleared during the term of validity of "Overflow signal" and "Compare match signal".
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For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer FH, timer FL interrupt might be repeated. (2 in figure 9.6) Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register F (TCSRF) after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. The term of validity of "Interrupt source generation signal" = 1 cycle of W + waiting time for completion of executing instruction + interrupt time synchronized with = 1/W + ST x (1/) + (2/) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3. After reading the timer control status register F (TCSRF), clear the timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Enable interrupts (set IENFH, IENFL to 1). Method 2 1. Set interrupt handling routine time to more than time that calculated with (1) formula. 2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). All above attentions are also applied in 16-bit mode and 8-bit mode.
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Section 9 Timers
Interrupt request flag clear 2 Program processing Interrupt Interrupt Normal Interrupt request flag clear
w Interrupt source generation signal (internal signal, nega-active) Overflow signal, compare match signal (internal signal, nega-active)
Interrupt request flag (IRRTFH, IRRTFL) 1
Figure 9.6 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid Timer Counter (TCF) Read/Write: When W/4 is selected as the internal clock in active (highspeed, medium-speed) mode, write on TCF is impossible. And when reading TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of 1. When reading or writing TCF in active (high-speed, medium-speed) mode is needed, please select the internal clock except for W/4 before read/write is performed. In subactive mode, even if W /4 is selected as the internal clock, TCF can be read from or written to normally.
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Section 9 Timers
9.4
Asynchronous Event Counter (AEC)
The asynchronous event counter is incremented by external event clock or internal clock input. Figure 9.7 shows a block diagram of the asynchronous event counter. 9.4.1 Features
* Can count asynchronous events Can count external events input asynchronously without regard to the operation of system clocks and SUB * Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter. * Event/clock input is enabled only when IRQAEC is high or event counter PWM output (IECPWM) is high. * Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM) interrupts. When the asynchronous counter is not used, they can be used as independent interrupts. * When an event counter PWM is used, event clock input enabling/disabling can be controlled automatically in a fixed cycle. * External event input or a prescaler output clock can be selected by software for the ECH and ECL clock sources. /2, /4, or /8 can be selected as the prescaler output clock. * Both edge counting is possible for AEVL and AEVH. * Counter resetting and halting of the count-up function can be controlled by software * Automatic interrupt generation on detection of an event counter overflow * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.)
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Section 9 Timers
IRREC PSS ECCR ECCSR
/2 /4, /8
OVH AEVH Edge sensing circuit OVL
ECH (8 bits)
CK
CK
AEVL IRQAEC
Edge sensing circuit Edge sensing circuit To CPU interrupt (IRREC2) ECPWCRL ECPWCRH
IECPWM
PWM waveform generator /2, /4, /8, /16, /32, /64 ECPWDRL ECPWDRH
AEGSR
Legend: ECPWCRH: ECPWDRH: AEGSR: ECCSR: ECL: Event counter PWM compare register H Event counter PWM data register H Input pin edge select register Event counter control/status register Event counter L ECPWCRL: ECPWDRL: ECCR: ECH: Event counter PWM compare register L Event counter PWM data register L Event counter control register Event counter H
Figure 9.7 Block Diagram of Asynchronous Event Counter
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Internal data bus
ECL (8 bits)
Section 9 Timers
9.4.2
Input/Output Pins
Table 9.5 shows the pin configuration of the asynchronous event counter. Table 9.5
Name
Pin Configuration
Abbreviation I/O Input Input Input Function Event input pin for input to event counter H Event input pin for input to event counter L Input pin for interrupt enabling event input
Asynchronous event input H AEVH Asynchronous event input L Event input enable interrupt input AEVL IRQAEC
9.4.3
Register Descriptions
The asynchronous event counter has the following registers. * * * * * * * * * Event counter PWM compare register H (ECPWCRH) Event counter PWM compare register L (ECPWCRL) Event counter PWM data register H (ECPWDRH) Event counter PWM data register L (ECPWDRL) Input pin edge select register (AEGSR) Event counter control register (ECCR) Event counter control/status register (ECCSR) Event counter H (ECH) Event counter L (ECL)
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Section 9 Timers
Event Counter PWM Compare Register H (ECPWCRH): ECPWCRH sets the one conversion period of the event counter PWM waveform.
Bit 7 6 5 4 3 2 1 0 Bit Name ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One conversion period of event counter PWM waveform
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCRH should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRH.
Event Counter PWM Compare Register L (ECPWCRL): ECPWCRL sets the one conversion period of the event counter PWM waveform.
Bit 7 6 5 4 3 2 1 0 Bit Name ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One conversion period of event counter PWM waveform
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCRL should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRL.
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Section 9 Timers
Event Counter PWM Data Register H (ECPWDRH): ECPWDRH controls data of the event counter PWM waveform generator.
Bit 7 6 5 4 3 2 1 0 Bit Name ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Data control of event counter PWM waveform generator
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWDRH should not be modified. When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRH.
Event Counter PWM Data Register L (ECPWDRL): ECPWDRL controls data of the event counter PWM waveform generator.
Bit 7 6 5 4 3 2 1 0 Bit Name ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Data control of event counter PWM waveform generator
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWDRL should not be modified. When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRL.
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Section 9 Timers
Input Pin Edge Select Register (AEGSR): AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins.
Bit 7 6 Bit Name AHEGS1 AHEGS0 Initial Value 0 0 R/W R/W R/W Description AEC Edge Select H Select rising, falling, or both edge sensing for the AEVH pin. 00: Falling edge on AEVH pin is sensed 01: Rising edge on AEVH pin is sensed 10: Both edges on AEVH pin are sensed 11: Setting prohibited 5 4 ALEGS1 ALEGS0 0 0 R/W R/W AEC Edge Select L Select rising, falling, or both edge sensing for the AEVL pin. 00: Falling edge on AEVL pin is sensed 01: Rising edge on AEVL pin is sensed 10: Both edges on AEVL pin are sensed 11: Setting prohibited 3 2 AIEGS1 AIEGS0 0 0 R/W R/W IRQAEC Edge Select Select rising, falling, or both edge sensing for the IRQAEC pin. 00: Falling edge on IRQAEC pin is sensed 01: Rising edge on IRQAEC pin is sensed 10: Both edges on IRQAEC pin are sensed 11: Setting prohibited 1 ECPWME 0 R/W Event Counter PWM Enable Controls operation of event counter PWM and selection of IRQAEC. 0: AEC PWM halted, IRQAEC selected 1: AEC PWM enabled, IRQAEC not selected 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1.
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Section 9 Timers
Event Counter Control Register (ECCR): ECCR controls the counter input clock and IRQAEC/IECPWM.
Bit 7 6 Bit Name ACKH1 ACKH0 Initial Value 0 0 R/W R/W R/W Description AEC Clock Select H Select the clock used by ECH. 00: AEVH pin input 01: /2 10: /4 11: /8 5 4 ACKL1 ACKL0 0 0 R/W R/W AEC Clock Select L Select the clock used by ECL. 00: AEVL pin input 01: /2 10: /4 11: /8 3 2 1 PWCK2 PWCK1 PWCK0 0 0 0 R/W R/W R/W Event Counter PWM Clock Select Select the event counter PWM clock. 000: /2 001: /4 010: /8 011: /16 1X0: /32 1X1 /64 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1. Legend: X: Don't care.
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Section 9 Timers
Event Counter Control/Status Register (ECCSR): ECCSR controls counter overflow detection, counter clear resetting, and the count-up function.
Bit 7 Bit Name OVH Initial Value 0 R/W R/W * Description Counter Overflow H This is a status flag indicating that ECH has overflowed. [Setting condition] When ECH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVH = 1 6 OVL 0 R/W * Counter Overflow L This is a status flag indicating that ECL has overflowed. [Setting condition] When ECL overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVL = 1 5 0 R/W Reserved This bit can be read from or written to. However, the initial value should not be changed. 4 CH2 0 R/W Channel Select Selects how ECH and ECL event counters are used 0: ECH and ECL are used together as a single-channel 16-bit event counter 1: ECH and ECL are used as two-channel 8-bit event counter 3 CUEH 0 R/W Count-Up Enable H Enables event clock input to ECH. 0: ECH event clock input is disabled (ECH value is retained) 1: ECH event clock input is enabled 2 CUEL 0 R/W Count-Up Enable L Enables event clock input to ECL. 0: ECL event clock input is disabled (ECL value is retained) 1: ECL event clock input is enabled
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Section 9 Timers Initial Value 0
Bit 1
Bit Name CRCH
R/W R/W
Description Counter Reset Control H Controls resetting of ECH. 0: ECH is reset 1: ECH reset is cleared and count-up function is enabled
0
CRCL
0
R/W
Counter Reset Control L Controls resetting of ECL. 0: ECL is reset 1: ECL reset is cleared and count-up function is enabled
Note:
*
Only 0 can be written to clear the flag.
Event Counter H (ECH): ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Bit 7 6 5 4 3 2 1 0 Bit Name ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVH pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software.
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Section 9 Timers
Event Counter L (ECL): ECL is an 8-bit read-only up-counter that operates as an independent 8bit event counter. ECL also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH.
Bit 7 6 5 4 3 2 1 0 Bit Name ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVL pin, /2, /4, or /8 can be selected as the input clock source. ECL can be cleared to H'00 by software.
9.4.4
Operation
16-Bit Counter Operation: When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources--/2, /4, /8, or AEVL pin input--can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 9.8 shows an example of the software processing when ECH and ECL are used as a 16-bit event counter.
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Section 9 Timers
Start
Clear CH2 to 0 Set ACKL1, ACKL0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.8 Example of Software Processing when Using ECH and ECL as 16-Bit Event Counter As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset, and as ACKL1 and ACKL0 are cleared to B00, the operating clock is asynchronous event input from the AEVL pin (using falling edge sensing). When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. 8-Bit Counter Operation: When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. /2, /4, /8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and /2, /4, /8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits ALEGS1 and ALEGS0 when AEVL pin input is selected. The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 9.9 shows an example of the software processing when ECH and ECL are used as 8-bit event counters.
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Section 9 Timers
Start
Set CH2 to 1 Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1, AHEGS0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.9 Example of Software Processing when Using ECH and ECL as 8-Bit Event Counters ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.9. When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. IRQAEC Operation: When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector addresses are H'000C and H'000D. Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1 and AIAGS0 in AEGSR.
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Section 9 Timers
Note: On the H8/38104 Group, control of switching between the system clock oscillator and the on-chip oscillator during resets should be performed by setting the IRQAEC input level. Refer to section 4.4, Subclock Generator, for details. Event Counter PWM Operation: When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL cannot be controlled individually. IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the vector addresses are H'000C and H'000D. Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits AIAGS1 and AIAGS0 in AEGSR. Figure 9.10 and table 9.6 show examples of event counter PWM operation.
Legend: ton: Clock input enable time toff: Clock input disable time tcm: One conversion period ECPWM input clock cycle T: Ndr: Value of ECPWDRH and ECPWDRL Fixed low when Ndr = H'FFFF Ncm: Value of ECPWCRH and ECPWCRL
toff = T * (Ndr +1)
ton
tcm = T * (Ncm +1)
Figure 9.10 Event Counter Operation Waveform Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
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Section 9 Timers
Table 9.6
Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, f = 2 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3
Clock Source Selection /2 /4 /8 /16 /32 /64 Note: * Clock Source ECPWMCR ECPWMDR Cycle (T)* Value (Ncm) Value (Ndr) 1 s 2 s 4 s 8 s 16 s 32 s toff minimum width H'7A11 D'31249 H'16E3 D'5859 toff = T * (Ndr + 1) 5.86 ms 11.72 ms 23.44 ms 46.88 ms 93.76 ms 187.52 ms tcm = T * (Ncm + 1) 31.25 ms 62.5 ms 125.0 ms 250.0 ms 500.0 ms 1000.0 ms ton = tcm - toff 25.39 ms 50.78 ms 101.56 ms 203.12 ms 406.24 ms 812.48 ms
Clock Input Enable/Disable Function Operation: The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending on the IRQAEC or IECPWM timing. Figure 9.11 shows an example of the operation of this function.
Input event
IRQAEC or IECPWM Edge generated by clock return Actually counted clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 9.11 Example of Clock Control Operation
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Section 9 Timers
9.4.5
Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 9.7. Table 9.7
Operating Mode
AEGSR ECCR ECCSR ECH ECL IRQAEC
Operating States of Asynchronous Event Counter
Reset
Reset Reset Reset Reset Reset Reset
Active
Functions Functions Functions Functions Functions Functions Functions
Sleep
Functions Functions Functions Functions Functions Functions Functions
Watch
Retained*1 Retained*1 Retained*1 Functions*1*2 Functions*1*2 Retained*3 Retained
Subactive
Functions Functions Functions
Sub-sleep Standby
Functions Functions Functions Retained*1 Retained*1 Retained*1
Module Standby
Retained Retained Retained Halted Halted Retained*4 Retained
Functions*2 Functions*2 Functions*1*2 Functions*2 Functions*2 Functions*1*2 Functions Retained Functions Retained Retained*3 Retained
Event counter Reset PWM
Notes: 1. When an asynchronous external event is input, the counter increments but the counter overflow H/L flags are not affected. 2. Functions when asynchronous external events are selected; halted and retained otherwise. 3. Clock control by IRQAEC operates, but interrupts do not. 4. As the clock is stopped in module standby mode, IRQAEC has no effect.
9.4.6
Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in 8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. 2. The maximum clock frequency that may be input to the AEVH and AEVL pins is 16 MHz*1. Furthermore, the clock high width and low width should be half or more the OSC clock cycle time. The duty ratio does not matter as long as the high width and low width satisfy the minimum requirement.
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Section 9 Timers Maximum Clock Frequency Input to AEVH/AEVL Pin 16 MHz* (/16) (/32) (/64) fOSC = 1 MHz to 4 MHz Watch, subactive, subsleep, standby W = 32.768 kHz or 38.4 kHz*2 (/128) (W /2) (W /4) (W /8) Notes: 1. Up to 10 MHz in the H8/38004, H8/38002S Group. 2. Does not apply to H8/38104 Group. 2 * fOSC fOSC 1/2 * fOSC 1/4 * fOSC 1000 kHz 500 kHz 250 kHz
1
Mode Active (high-speed), sleep (high-speed) Active (medium-speed), sleep (medium-speed)
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1 second, or set both CUEH and CRCH to 1 at same time before clock input. While AEC is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up. 4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCRH, ECPWCRL, ECPWDRH, and ECPWDRL should not be modified. When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying these registers. 5. The event counter PWM data register and event counter PWM compare register must be set so that event counter PWM data register < event counter PWM compare register. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR. 6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
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Section 9 Timers
9.5
Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. However, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the implementation differs in the H8/38004, H8/38002S Group and the H8/38104 Group. 9.5.1 Features
* Selectable from two counter input clocks (H8/38004, H8/38002S Group). Two clock sources (/8192 or W/32) can be selected as the timer-counter clock. * On the H8/38104 Group, 10 internal clocks are available for selection. Ten internal clocks (/64, /128, /256, /512, /1024, /2048, /4096, /8192, w/32, or watchdog on-chip oscillator) can be selected as the timer-counter clock. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.)
w/32
TCSRW
PSS
/8192
TCW
Legend: TCSRW: Timer control/status register W TCW: Timer counter W PSS: Prescaler S
Internal reset signal
Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004, H8/38002S Group)
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Internal data bus
Section 9 Timers
TMW
TCSRW
PSS
TCW
W/32 Interrupt/reset controller
Internal data bus
Watchdog on-chip oscillator
Internal reset signal or interrupt request signal
Legend: TCSRW: TCW: TMW: PSS:
Timer control/status register W Timer counter W Timer mode register W Prescaler S
Figure 9.12(2) Block Diagram of Watchdog Timer (H8/38104 Group) 9.5.2 Register Descriptions
The watchdog timer has the following registers. * Timer control/status register W (TCSRW) * Timer counter W (TCW) * Timer mode register W (TMW)* Note: * This register is implemented on the H8/38104 Group only. Timer Control/Status Register W (TCSRW): TCSRW performs the TCSRW and TCW write control. TCSRW also controls the watchdog timer operation and indicates the operating state. TCSRW must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
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Section 9 Timers Initial Value 1
Bit 7
Bit Name B6WI
R/W R
Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0.
6
TCWE
0
This bit is always read as 1. R/(W)*1 Timer Counter W Write Enable TCW can be written when the TCWE bit is set to 1. When writing data to this bit, the value for bit 7 must be 0.
5
B4WI
1
R
Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1.
4
TCSRWE
0
R/(W)*1 Timer Control/Status Register W Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0.
3
B2WI
1
R
Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0.
2
WDON
0/1*2
This bit is always read as 1. R/(W)*1 Watchdog Timer On TCW starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing condition] * When 0 is written to the WDON bit while writing 0 to the B2WI when the TCSRWE bit=1 * Reset by pin*3
1
B0WI
1
R
Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1.
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SER
Section 9 Timers Initial Value 0
Bit 0
Bit Name WRST
R/W R/(W) *1
Description Watchdog Timer Reset [Setting condition] When TCW overflows and an internal reset signal is generated [Clearing condition] * When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit = 1 * Reset by pin
Notes: 1. These bits can be written only when the writing conditions are satisfied. 2. Initial value 0 on H8/38004, H8/38002S Group and 1 on H8/38104 Group. 3. On reset, cleared to 0 on H8/38004, H8/38002S Group and set to 1 on H8/38104 Group.
Timer Counter W (TCW): TCW is an 8-bit readable/writable up-counter. When TCW overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRW is set to 1. TCW is initialized to H'00. Timer Mode Register W (TMW): TMW selects the input clock. Clock source selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to 0. If WDCKS is set to 1, w/32 is selected as the clock source, regardless of the setting of TMW. Note: TMW is implemented on H8/38104 Group only.
SER
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Section 9 Timers Initial Value All 1 1 1 1 1
Bit 7 to 4 3 2 1 0
Bit Name -- CKS3 CKS2 CKS1 CKS0
R/W -- R/W R/W R/W R/W
Description This bit is reserved. It is always read as 1. Clock Select 3 to 0 Selects the clock input to TCWD. 1000: Internal clock: counting on /64 1001: Internal clock: counting on /128 1010: Internal clock: counting on /256 1011: Internal clock: counting on /512 1100: Internal clock: counting on /1,024 1101: Internal clock: counting on /2,048 1110: Internal clock: counting on /4,096 1111: Internal clock: counting on /8,192 0XXX: On-chip oscillator See section 17, Electrical Characteristics, for information on the overflow period of the on-chip oscillator.
Legend:
X: Don't care
9.5.3
Operation
The watchdog timer is provided with an 8-bit counter. The input clock is selected by the WDCKS bit in the port mode register 2 (PMR2)*: On the H8/38004, H8/38002S Group, /8192 is selected when the WDCKS bit is cleared to 0, and w/32 when set to 1. On the H8/38104 Group, the clock specified by timer mode register W (TMW) is selected when WDCKS is cleared to 0, and w/32 is selected when WDCKS is set to 1. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRW is set to 1, TCW begins counting up. (To operate the watchdog timer, two write accesses to TCSRW are required. However, on the H8/38104 Group, TCW begins counting up even if no write access occurs, because WDON is set to 1 when the reset is cleared.) When a clock pulse is input after the TCW count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 512 osc clock cycles. TCW is a writable counter, and when a value is set in TCW, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCW set value. Note: * For details, refer to section 8.1.5, Port Mode Register 2 (PMR2).
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Section 9 Timers
Figure 9.13 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when = 4 MHz 4 * 106 8192
* 30 * 10-3 = 14.6
Therefore, 256 - 15 = 241 (H'F1) is set in TCW. TCW overflow
H'FF H'F1 TCW count value
H'00 Start H'F1 written to TCW Internal reset signal 512 osc clock cycles H'F1 written to TCW Reset generated
Figure 9.13 Example of Watchdog Timer Operation
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Section 9 Timers
9.5.4
Operating States of Watchdog Timer
Tables 9.8(1) and 9.8(2) summarize the operating states of the watchdog timer for the H8/38004, H8/38002S Group and H8/38104 Group, respectively. Table 9.8(1) Operating States of Watchdog Timer (H8/38004, H8/38002S Group)
Operating Mode
TCW
Reset
Reset
Active
Functions
Sleep
Functions
Watch
Halted
Sub-active Sub-sleep
Functions/ Halted* Halted
Standby
Halted
Module Standby
Halted
TCSRW
Reset
Functions
Functions
Retained
Functions/ Halted*
Retained
Retained
Retained
Note:
*
Functions when W /32 is selected as the input clock.
Table 9.8(2) Operating States of Watchdog Timer (H8/38104 Group)
Operating Mode TCW Reset Reset Active Functions Sleep Functions Watch Functions/ Halted*1 Sub-active Functions/ Halted*1 Sub-sleep Functions/ Halted*1 Functions/ Retained*1 Functions/ Retained*1 Standby Functions/ Halted*2 Functions/ Retained*2 Functions/ Retained*2 Module Standby Halted
TCSRW
Reset
Functions
Functions
Functions/ Functions/ Retained*1 Halted*1 Functions/ Functions/ Retained*1 Halted*1
Retained
TMW
Reset
Functions
Functions
Retained
Notes: 1. Functions when w/32 or the on-chip clock oscillator is selected as the internal clock. 2. Functions only when the on-chip clock oscillator is selected.
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Section 10 Serial Communication Interface 3 (SCI3)
Section 10 Serial Communication Interface 3 (SCI3)
Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Figure 10.1 shows a block diagram of the SCI3.
10.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * External clock or on-chip baud rate generator can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. Note: On the H8/38104 Group, the system clock generator must be used when carrying out this function. Asynchronous mode * * * * * Data length: 7, 8, or 5 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD32 pin level directly in the case of a framing error
SCI0012A_000020020900
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Section 10 Serial Communication Interface 3 (SCI3)
Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected
SCK32
External clock Baud rate generator
Internal clock (/64, /16, w/2, )
BRC Clock
BRR
Transmit/receive control circuit
SCR3 SSR
TXD32 SPCR RXD32
TSR
TDR
RSR
RDR Interrupt request (TEI, TXI, RXI, ERI)
Legend: RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: SPCR:
Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Serial port control register
Figure 10.1 Block Diagram of SCI3
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Internal data bus
SMR
Section 10 Serial Communication Interface 3 (SCI3)
10.2
Input/Output Pins
Table 10.1 shows the SCI3 pin configuration. Table 10.1 Pin Configuration
Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation SCK32 RXD32 TXD32 I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output
10.3
Register Descriptions
The SCI3 has the following registers. * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR) Serial port control register (SPCR) Receive Shift Register (RSR)
10.3.1
RSR is a shift register that is used to receive serial data input from the RXD32 pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00 at a reset and in standby, watch, or module standby mode. 10.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD32 pin. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU. 10.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF at a reset and in standby, watch, or module standby mode.
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI3's serial transfer format and select the on-chip baud rate generator clock source. SMR is initialized to H'00 at a reset and in standby, watch, or module standby mode.
Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 or 5 bits as the data length. 1: Selects 7 or 5 bits as the data length. When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted. To select 5 bits as the data length, set 1 to both the PE and MP bits. The three most significant bits (bits 7, 6, and 5) in TDR are not transmitted. In clocked synchronous mode, the data length is fixed to 8 bits regardless of the CHR bit setting. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In clocked synchronous mode, parity bit addition and checking is not performed regardless of the PE bit setting.
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Section 10 Serial Communication Interface 3 (SCI3) Initial Value 0
Bit 4
Bit Name PM
R/W R/W
Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. If parity bit addition and checking is disabled in clocked synchronous mode and asynchronous mode, the PM bit setting is invalid.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
2
MP
0
R/W
Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid. In clocked synchronous mode, this bit should be cleared to 0.
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Section 10 Serial Communication Interface 3 (SCI3) Initial Value 0 0
Bit 1 0
Bit Name CKS1 CKS0
R/W R/W R/W
Description Clock Select 0 and 1 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: w/2 or w clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) When the setting value is 01 in active mode and sleep mode, w/2 clock is set. In subactive mode and subsleep mode, w clock is set. The SCI3 is enabled only when w /2 is selected for the CPU operating clock. For the relationship between the bit rate register setting and the baud rate, see section 10.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 10.3.8, Bit Rate Register (BRR)).
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. SCR3 is initialized to H'00 at a reset and in standby, watch, or module standby mode. For details on interrupt requests, refer to section 10.7, Interrupts.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. TXI can be released by clearing the TDRE bit or TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing bit RIE to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. When this bit is 0, the TDRE bit in SSR is fixed at 1. When transmit data is written to TDR while this bit is 1, bit TDRE in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out SMR settings, and setting of bit SPC32 in SPCR, to decide the transmission format before setting bit TE to 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. Be sure to carry out the SMR settings to decide the reception format before setting bit RE to 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state.
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Section 10 Serial Communication Interface 3 (SCI3) Initial Value 0
Bit 3
Bit Name MPIE
R/W R/W
Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 10.6, Multiprocessor Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable When this bit is set to 1, the TEI interrupt request is enabled. TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0.
1 0
CKE1 CKE0
0 0
R/W R/W
Clock Enable 0 and 1 Selects the clock source. Asynchronous mode: 00: Internal baud rate generator 01: Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK32 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK32 pin. 11:Reserved Clocked synchronous mode: 00: Internal clock (SCK32 pin functions as clock output) 01:Reserved 10: External clock (SCK32 pin functions as clock input) 11:Reserved
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is initialized to H'84 at a reset and in standby, watch, or module standby mode.
Bit 7 Bit Name TDRE Initial Value 1 R/W Description
R/(W)* Transmit Data Register Empty Indicates that transmit data is stored in TDR. [Setting conditions] * * * When the TE bit in SCR3 is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1
[Clearing conditions] * When the transmit data is written to TDR R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When data is read from RDR
6
RDRF
0
[Clearing conditions] * *
If an error is detected in reception, or if the RE bit in SCR3 has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will occur and the receive data will be lost.
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Section 10 Serial Communication Interface 3 (SCI3) Initial Value 0
Bit 5
Bit Name OER
R/W
Description
R/(W)* Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition] When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state. When an overrun error occurs, RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in clocked synchronous mode, transmission cannot be continued either.
4
FER
0
R/(W)* Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition] When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous state. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs, the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In clocked synchronous mode, neither transmission nor reception is possible when bit FER is set to 1.
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Section 10 Serial Communication Interface 3 (SCI3) Initial Value 0
Bit 3
Bit Name PER
R/W
Description
R/(W)* Parity Error [Setting condition] * * When a parity error is generated during reception When 0 is written to PER after reading PER = 1 [Clearing condition] When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous state. Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In clocked synchronous mode, neither transmission nor reception is possible when bit PER is set to 1.
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR3 is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions] * * 1 MPBR 0 R
Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR3 is cleared to 0, its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data.
Note:
*
Only 0 can be written for clearing a flag.
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.8
Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF at a reset and in standby, watch, or module standby mode. Table 10.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 10.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 10.2 and 10.4 are values in active (high-speed) mode. Table 10.5 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in clocked synchronous mode. The values are shown in table 10.5. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode]
N= 32 * 22n * B -1
Error (%) =
B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 10.2) R (bit rate in left-hand column in table 10.2)
* 100
Legend:
B: N: : n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.3.)
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
16.4 kHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n -- -- -- 0 -- -- N -- -- -- 1 -- -- Error (%) -- -- -- 2.5 -- -- n -- 0 0 -- 0 0 -- 19.45 kHz N -- 3 2 -- 1 0 -- Error (%) -- 0 0 -- 0 0 -- n 2 2 2 3 0 0 0 0 -- -- -- 0 -- 1 MHz N 17 12 9 1 103 51 25 12 -- -- -- 0 -- Error (%) -1.36 0.16 -2.34 -2.34 0.16 0.16 0.16 0.16 -- -- -- 0 -- n 2 3 3 0 3 3 2 2 0 0 0 -- 0 1.2288 MHz N 21 3 2 153 1 0 1 0 7 3 1 -- 0 Error (%) -0.83 0 0 -0.26 0 0 0 0 0 0 0 -- 0
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
2 MHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 3 2 2 0 0 0 0 -- -- 0 -- N 8 25 4 15 12 Error (%) -1.36 0.16 -2.34 -2.34 0.16 n 3 3 3 3 3 3 3 3 2 2 0 0 0 5 MHz N 21 15 11 9 7 3 1 0 1 0 7 4 3 Error (%) 0.88 1.73 1.73 -2.34 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 n 3 3 3 3 3 2 2 0 0 0 0 0 -- 8 MHz N 35 25 19 15 12 25 12 103 51 25 12 7 -- Error (%) -1.36 0.16 -2.34 -2.34 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -- n 3 3 3 3 3 3 3 3 3 2 2 0 0 10 MHz N 43 32 23 19 15 7 3 1 0 1 0 9 7 Error (%) 0.88 -1.36 1.73 -2.34 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73
103 0.16 51 25 12 -- -- 1 -- 0.16 0.16 0.16 -- -- 0 --
Legend: No indication: Setting not possible. : A setting is available but error occurs
Table 10.3 Relation between n and Clock
SMR Setting n 0 0 2 3 Clock W /2 /W *1 /16 /64 *2 CKS1 0 0 1 1 CKS0 0 1 0 1
Notes: 1. W /2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode 2. W clock in subactive mode and subsleep mode In subactive or subsleep mode, the SCI3 can be operated when CPU clock is W /2 only.
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting OSC (MHz) 0.0384* 2 2.4576 4 10 16 20 Note: * (MHz) 0.0192 1 1.2288 2 5 8 10 Maximum Bit Rate (bit/s) 600 31250 38400 62500 156250 250000 312500 n 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0
When CKS1 = 0 and CKS0 = 1 in SMR
Table 10.5 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)
19.2 kHz Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M n 0 -- 2 N 23 -- 0 Error (%) 0 -- 0 n -- -- -- -- 0 0 0 0 0 0 -- 0 1 MHz N -- -- -- -- 249 99 49 24 9 4 -- 0 Error (%) -- -- -- -- 0 0 0 0 0 0 -- 0 n -- 2 -- -- -- 0 0 0 0 0 0 0 0 2 MHz N -- 124 -- -- -- 199 99 49 19 9 4 1 0 Error (%) -- 0 -- -- -- 0 0 0 0 0 0 0 0
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.5 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)
Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 5 MHz n -- -- -- -- -- -- 0 0 0 0 -- 0 -- -- N -- -- -- -- -- -- 249 124 49 24 -- 4 -- -- Error (%) -- -- -- -- -- -- 0 0 0 0 -- 0 -- -- n -- 3 -- 2 2 2 2 0 0 0 0 0 0 0 8 MHz N -- 124 -- 249 124 49 24 199 79 39 19 7 3 1 Error (%) -- 0 -- 0 0 0 0 0 0 0 0 0 0 0 n 0 2 0 0 0 0 0 0 0 0 0 0 0 -- N 12499 624 8332 4999 2499 999 499 249 99 49 24 9 4 -- 10 MHz Error (%) 0 0 0 0 0 0 0 0 0 0 0 0 0 --
Legend: Blankx: No setting is available. --: A setting is available but error occurs. Note: The value set in BRR is given by the following formula:
N= 8 * 22n * B -1
B: N: : n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.6.)
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.6 Relation between n and Clock
SMR Setting n 0 0 2 3 Clock W /2*1/W *2 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
Notes: 1. W /2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode 2. W clock in subactive mode and subsleep mode In subactive or subsleep mode, the SCI3 can be operated when CPU clock is W /2 only.
10.3.9
Serial Port Control Register (SPCR)
SPCR selects whether input/output data of the RXD32 and TXD32 pins is inverted or not.
Bit 7, 6 5 Bit Name SPC32 Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. P42/TXD32 Pin Function Switch This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. 0: P42 I/O pin 1: TXD32 output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1. 4 3 SCINV3 0 W R/W Reserved The write value should always be 0. TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 pin output data is inverted. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted
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Section 10 Serial Communication Interface 3 (SCI3) Initial Value 0
Bit 2
Bit Name SCINV2
R/W R/W
Description RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 pin input data is inverted. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted
1, 0
W
Reserved The write value should always be 0.
Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
10.4
Operation in Asynchronous Mode
Figure 10.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. Table 10.7 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in SMR as shown in table 10.8.
LSB Serial Start data bit Transmit/receive data MSB Parity bit Stop bit 1 Mark state
1 bit
5, 7, or 8 bits
1 bit, or none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 10.2 Data Format in Asynchronous Communication
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Section 10 Serial Communication Interface 3 (SCI3)
10.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK32 pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. For details on selection of the clock source, see table 10.9. When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can be output from the SCK32 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.3.
Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 10.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.7 Data Transfer Formats (Asynchronous Mode)
SMR CHR 0 PE 0 MP 0 STOP 0 1
START
Serial Data Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data
0
0
0
1
START
8-bit data
STOP
STOP
0
0
1
0
START
8-bit data
MPB
STOP
0
0
1
1
START
8-bit data
MPB
STOP
STOP
0
1
0
0
START
8-bit data
P
STOP
0
1
0
1
START
8-bit data
P
STOP
STOP
0
1
1
0
START
5-bit data
STOP
0
1
1
1
START
5-bit data
STOP
STOP
1
0
0
0
START
7-bit data
STOP
1
0
0
1
START
7-bit data
STOP
STOP
1
0
1
0
START
7-bit data
MPB
STOP
1
0
1
1
START
7-bit data
MPB
STOP
STOP
1
1
0
0
START
7-bit data
P
STOP
1
1
0
1
START
7-bit data
P
STOP
STOP
1
1
1
0
START
5-bit data
P
STOP
1 Legend:
1
1
1
START
5-bit data
P
STOP
STOP
Don't care *: START: Start bit
STOP: Stop bit P: MPB Parity bit Multiprocessor bit
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.8 SMR Settings and Corresponding Data Transfer Formats
SMR Bit 7 COM 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 * * Clocked synchronous mode 8-bit data No No 5-bit data No Yes 7-bit data Yes 5-bit data No 8-bit data Yes No Yes 7-bit data No Mode Data Length Data Transfer Format Multiprocessor Bit Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No
Asynchronous 8-bit data No mode
Legend:
*: Don't care
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR Bit 7 COM 0 Bit 1 CKE1 0 SCR3 Bit 0 CKE0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 Mode Asynchronous mode Transmit/Receive Clock Clock Source Internal SCK32 Pin Function I/O port (SCK32 pin not used) Outputs clock with same frequency as bit rate External Internal Clocked synchronous mode External Inputs clock with frequency 16 times bit rate Outputs serial clock Inputs serial clock
Reserved (Do not specify these combinations)
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Section 10 Serial Communication Interface 3 (SCI3)
10.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 10.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. When the external clock is used in clocked synchronous mode, the clock must not be supplied during initialization.
[1] Start initialization Set the clock selection in SCR3. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] [3] No 1-bit interval elapsed? Yes Set SPC32 bit in SPCR to 1 Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. [4] [4] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. Setting bits TE and RE enables the TXD32 and RXD32 pins to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.
Clear TE and RE bits in SCR3 to 0 [1] Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR Wait
[3]

Figure 10.4 Sample SCI3 Initialization Flowchart
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Section 10 Serial Communication Interface 3 (SCI3)
10.4.3
Data Transmission
Figure 10.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. 2. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. The SCI3 checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. Figure 10.6 shows a sample flowchart for transmission in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1
3. 4. 5.
6.
TDRE TEND LSI TXI interrupt operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI interrupt request generated TEI interrupt request generated
Figure 10.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 10 Serial Communication Interface 3 (SCI3)
Start transmission Set SPC32 bit in SPCR to 1
[1]
Read TDRE flag in SSR
No TDRE = 1 Yes
Write transmit data to TDR
[2]
Yes All data transmitted? No
[1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. (After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.) [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear the TE bit in SCR3 to 0.
Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes Clear PDR to 0 and set PCR to 1
[3]
Clear TE bit in SCR3 to 0
Figure 10.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
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Section 10 Serial Communication Interface 3 (SCI3)
10.4.4
Serial Data Reception
Figure 10.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
* Parity check The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
3. 4.
5.
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Section 10 Serial Communication Interface 3 (SCI3)
Start bit Serial data 1 0 D0 D1
Receive data D7 1 frame
Parity Stop Start bit bit bit 0/1 1 0 D0
Receive data D1 1 frame D7
Parity Stop bit bit 0/1 0
Mark state (idle state) 1
RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 stop bit detected ERI request in response to framing error Framing error processing
Figure 10.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Table 10.10 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.8 shows a sample flowchart for serial data reception. Table 10.10 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Receive Error Type Overrun error
Transferred to RDR Framing error Transferred to RDR Parity error Lost Lost Overrun error + framing error Overrun error + parity error
Transferred to RDR Framing error + parity error Lost Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the RDRF flag will be cleared to 0.
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Section 10 Serial Communication Interface 3 (SCI3)
[1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RXD32 pin.
Start reception
Read OER, PER, and FER flags in SSR
[1]
Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2]
Read receive data in RDR
Yes All data received? (A) No Clear RE bit in SCR3 to 0 [3]
Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
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[4] Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing
No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0

Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)
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10.5
Operation in Clocked Synchronous Mode
Figure 10.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
8-bit One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 10.9 Data Format in Clocked Synchronous Communication 10.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK32 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock, the serial clock is output from the SCK32 pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 10.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 10.4.
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10.5.3
Serial Data Transmission
Figure 10.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. 2. 3. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 8-bit data is sent from the TXD32 pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD32 pin. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. The SCK32 pin is fixed high.
4. 5. 6.
7.
Figure 10.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
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Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR
1 frame
TXI interrupt request generated
TEI interrupt request generated
Figure 10.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
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Start transmission
Set SPC32 bit in SPCR to 1
[1]
[1]
Read TDRE flag in SSR
No TDRE = 1 [2] Yes
Write transmit data to TDR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When clock output is selected and data is written to TDR, clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
[2]
All data transmitted? No
Yes
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR3 to 0
Figure 10.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
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10.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 10.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. The SCI3 stores the received data in RSR. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated.
4.
Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read
1 frame
RXI interrupt request generated
ERI interrupt request generated by overrun error Overrun error processing
RDR data has not been read (RDRF = 1)
Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.13 shows a sample flowchart for serial data reception.
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Start reception [1] Read OER flag in SSR [1] [2] Yes OER = 1 [4] No Error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1 Yes [3] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1.
No
Read receive data in RDR
Yes All data received? No Clear RE bit in SCR3 to 0 [3]
[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0
Figure 10.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
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Section 10 Serial Communication Interface 3 (SCI3)
10.5.5
Simultaneous Serial Data Transmission and Reception
Figure 10.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Start transmission/reception
Set SPC32 bit in SPCR to 1
[1]
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR
[1]
Read OER flag in SSR Yes [4] Error processing
OER = 1 No
Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR
[2]
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 10.13.
Yes All data received? No [3]
Clear TE and RE bits in SCR to 0

Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
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Section 10 Serial Communication Interface 3 (SCI3)
10.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 10.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend: MPB: Multiprocessor bit
Figure 10.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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10.6.1
Multiprocessor Serial Data Transmission
Figure 10.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Start transmission
Set SPC32 bit in SPCR to 1 [1] [1] Read TDRE flag in SSR Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR3 to 0.
No TDRE = 1 [2] Yes
Set MPBT bit in SSR
[3] Write transmit data to TDR
Yes [2] All data transmitted? No
Read TEND flag in SSR
No TEND = 1 Yes No [3] Break output? Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0

Figure 10.16 Sample Multiprocessor Serial Transmission Flowchart
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10.6.2
Multiprocessor Serial Data Reception
Figure 10.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 10.18 shows an example of SCI3 operation for multiprocessor format reception.
Start reception
[1] [2] [1] [3]
Set MPIE bit in SCR3 to 1
Read OER and FER flags in SSR
[2] Yes
FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read OER and FER flags in SSR Yes FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR [4] [3] [4] [5]
Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD32 pin value.
[5] Error processing (Continued on next page)
Yes
All data received? No [A] Clear RE bit in SCR3 to 0
Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (1)
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[5]
Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing [A]
Clear OER, and FER flags in SSR to 0

Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 10 Serial Communication Interface 3 (SCI3)
Start bit Serial data 1 0 D0 Receive data (ID1) D1 1 frame D7 Stop Start bit bit 1 0 D0 Receive data (Data1) D1 1 frame D7 Stop bit 1 Mark state (idle state) 1
MPB 1
MPB 0
MPIE
RDRF RDR value LSI operation User processing RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again ID1
RXI interrupt request is not generated, and RDR retains its state
(a) When data does not match this receiver's ID
Start bit Serial data 1 0 D0
Receive data (ID2) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data2) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing ID1 ID2 Data2
RXI interrupt request MPIE cleared to 0
RDRF flag cleared to 0 RDR data read
RXI interrupt request When data is this station's ID, reception is continued
RDRF flag cleared to 0 RDR data read MPIE set to 1 again
(b) When data matches this receiver's ID
Figure 10.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 10 Serial Communication Interface 3 (SCI3)
10.7
Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 10.11 shows the interrupt sources. Table 10.11 SCI3 Interrupt Requests
Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, or PER in SSR Enable Bit RIE TIE TEIE RIE
Each interrupt request can be enabled or disabled by means of bits TIE, RIE and TEIE in SCR3. When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in SSR, a TEI interrupt is requested. These two interrupts are generated during transmission. The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR. When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during reception. For further details, see section 3, Exception Handling. The SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.12.
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.12 Transmit/Receive Interrupts
Flag and Enable Bit Interrupt Request Conditions RDRF RIE When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, RXI is enabled and an interrupt is requested. (See figure 10.19(a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, TXI is enabled and an interrupt is requested. (See figure 10.19(b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, TEI is enabled and an interrupt is requested. (See figure 10.19(c).)
Interrupt RXI
Notes The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. TEI indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is transmitted.
TXI
TDRE TIE
TEI
TEND TEIE
RDR
RDR
RSR (reception in progress) RXD32 pin RXD32 pin
RSR (reception completed, transfer)
RDRF = 0
RDRF
(RXI request when RIE = 1)
Figure 10.19(a) RDRF Setting and RXI Interrupt
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Section 10 Serial Communication Interface 3 (SCI3)
TDR (next transmit data) TDR
TSR (transmission in progress) TXD32 pin TXD32 pin
TSR (transmission completed, transfer)
TDRE = 0
TDRE
(TXI request when TIE = 1)
Figure 10.19(b) TDRE Setting and TXI Interrupt
TDR TDR
TSR (transmission in progress) TXD32 pin TXD32 pin
TSR (transmission completed)
TEND = 0
TEND
(TEI request when TEIE = 1)
Figure 10.19(c) TEND Setting and TEI Interrupt
10.8
10.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD32 pin value directly. In a break, the input from the RXD32 pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 10.8.2 Mark State and Break Sending
When TE is 0, the TXD32 pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TXD32 pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD32 pin becomes an I/O port, and 1 is output from the TXD32 pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the
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1
Section 10 Serial Communication Interface 3 (SCI3)
transmitter is initialized regardless of the current transmission state, the TXD32 pin becomes an I/O port, and 0 is output from the TXD32 pin. 10.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 10.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.20. Thus, the reception margin in asynchronous mode is given by formula (1) below.
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F * 100(%) 2N N
... Formula (1) Where N D L F : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0.5 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 * 16)} * 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
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16 clocks 8 clocks 0 Internal basic clock Receive data (RXD32) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 10.20 Receive Data Sampling Timing in Asynchronous Mode 10.8.5 Note on Switching SCK32 Function
If pin SCK32 is used as a clock output pin by the SCI3 in clocked synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. a. When an SCK32 function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK32 from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should be pulled up to the VCC level via a resistor, or supplied with output from an external device. b. When an SCK32 function is switched from clock output to general input/output When stopping data transfer, (i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. (ii) Clear bit COM in SMR to 0 (iii) Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to SCK32.
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10.8.6
Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not two or more times). 10.8.7 Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is shown in figure 10.21.
Frame 1 Frame 2 Frame 3
Communication line
Data 1
Data 2
Data 3
RDRF
RDR
Data 1 (A)
RDR read
Data 2 (B)
RDR read
Data 1 is read at point (A) Data 2 is read at point (B)
Figure 10.21 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
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Section 10 Serial Communication Interface 3 (SCI3)
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clocked synchronous mode, or before the STOP bit is transferred in asynchronous mode. 10.8.8 Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 10.8.9 Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is W/2. The SA1 bit in SYSCR2 should be set to 1. 10.8.10 Oscillator Use with Serial Communication Interface 3 in Asynchronous Mode (H8/38104 Group Only) When implementing serial communication interface 3 in asynchronous mode on the H8/38104 Group, the system clock oscillator must be used. The on-chip oscillator should not be used in this case. See section 4.3.4, On-Chip Oscillator Selection Method, for information on switching between the system clock oscillator and the on-chip oscillator.
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Section 10 Serial Communication Interface 3 (SCI3)
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Section 11 10-Bit PWM
Section 11 10-Bit PWM
This LSI has a two-channel 10-bit PWM. The PWM with a low-path filter connected can be used as a D/A converter. Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/3802 Group, H8/38004 Group and H8/38002S Group. Figure 11.1(2) shows a block diagram of the 10bit PWM of the H8/38104 Group.
11.1
Features
* Choice of four conversion periods A conversion period of 4096/ with a minimum modulation width of 4/, a conversion period of 2048/ with a minimum modulation width of 2/, a conversion period of 1024/ with a minimum modulation width of 1/, or a conversion period of 512/ with a minimum modulation width of 1/2 can be selected. * Pulse division method for less ripple * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) * On the H8/38104 Group it is possible to select between two types of PWM output: pulsedivision 10-bit PWM and event counter PWM (PWM incorporating AEC). (The H8/3802 Group, H8/38004 Group and H8/38002S Group can only produce 10-bit PWM output.) Refer to section 9.4, Asynchronous Event Counter, for information on event counter PWM.
PWM1000A_000020020900
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Section 11 10-Bit PWM
PWCR
Internal data bus
PWDRL
PWDRU
/8 /4 /2 Legend: PWCR: PWDRL: PWDRU: PWM:
PWM waveform generator
PWM
PWM control register PWM data register L PWM data register U PWM output pin
Figure 11.1(1) Block Diagram of 10-Bit PWM (H8/3802 Group, H8/38004 Group, H8/38002S Group)
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Section 11 10-Bit PWM
PWCR
PWDRL
PWDRU
/8 /4 /2
PWM waveform generator
Internal data bus
PWM (IECPWM)
IECPWM Legend: PWCR: PWDRL: PWDRU: PWM: IECPWM:
PWM control register PWM data register L PWM data register U PWM output pin Event counter PWM (PWM incorporating AEC)
Figure 11.1(2) Block Diagram of 10-Bit PWM (H8/38104 Group)
11.2
Input/Output Pins
Table 11.1 shows the 10-bit PWM pin configuration. Table 11.1 Pin Configuration
Name 10-bit PWM square-wave output 1 10-bit PWM square-wave output 2 Abbreviation PWM1 I/O Output Function Channel 1: 10-bit PWM waveform output pin/event counter PWM output pin* Channel 2: 10-bit PWM waveform output pin/event counter PWM output pin*
PWM2
Output
Note: * The event counter PWM output pin is valid on the H8/38104 Group only.
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Section 11 10-Bit PWM
11.3
Register Descriptions
The 10-bit PWM has the following registers. * PWM control register (PWCR) * PWM data register U (PWDRU) * PWM data register L (PWDRL) 11.3.1 PWM Control Register (PWCR)
On the H8/3802 Group, H8/38004 Group and H8/38002S Group, PWCR selects the conversion period.
Bit 7 6 5 4 3 2 1 0 Bit Name PWCR1 PWCR0 Initial Value 1 1 1 1 1 1 0 0 R/W W W Clock Select 1, 0 00: The input clock is (t = 1/) The conversion period is 512/, with a minimum modulation width of 1/2 01: The input clock is /2 (t = 2/) The conversion period is 1024/, with a minimum modulation width of 1/ 10: The input clock is /4 (t = 4/) The conversion period is 2048/, with a minimum modulation width of 2/ 11: The input clock is /8 (t = 8/) The conversion period is 4096/, with a minimum modulation width of 4/ Legend: t: Period of PWM clock input Description Reserved These bits are always read as 1, and cannot be modified.
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Section 11 10-Bit PWM
Selects the PWCR output format and the conversion period on the H8/38104 Group.
Bit 7 6 5 4 3 2 Bit Name PWCR2 Initial Value 1 1 1 1 1 0 R/W W Output Format Select 0: 10-bit PWM 1: Event counter PWM (PWM incorporating AEC) 1 0 PWCR1 PWCR0 0 0 W W Clock Select 1, 0 00: The input clock is (t = 1/) -- The conversion period is 512/, with a minimum modulation width of 1/2 01: The input clock is /2 (t = 2/) -- The conversion period is 1,024/, with a minimum modulation width of 1/ 10: The input clock is /4 (t = 4/) -- The conversion period is 2,048/, with a minimum modulation width of 2/ 11: The input clock is /8 (t = 8/) -- The conversion period is 4,096/, with a minimum modulation width of 4/ Legend: t: Period of PWM clock input Description Reserved This bit is reserved. It is always read as 1 and cannot be written to.
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Section 11 10-Bit PWM
11.3.2
PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 10-bit write-only registers, with the upper 2 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed. When 10-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. When writing the 10-bit data, the order is as follows: PWDRL to PWDRU. PWDRU and PWDRL are initialized to H'FC00.
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Section 11 10-Bit PWM
11.4
11.4.1
Operation
Operation
When using the 10-bit PWM, set the registers in this sequence: 1. Set the PWM2 and/or PWM1 bits in port mode register 9 (PMR9) to 1 to set the P91/PWM2 pin or P90/PWM1 pin, or both, to function as PWM output pins. 2. Set the PWCR0 and PWCR1 bits in PWCR to select a conversion period of either. On the H8/38104 Group, the output format is selected using the PWCR2 bit. Refer to section 9.4, Asynchronous Event Counter, for information on how to select event counter PWM (PWM incorporating AEC), one of the two available output formats. 3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these registers are latched in the PWM waveform generator, and the PWM waveform generation data is updated in synchronization with internal signals. One conversion period consists of four pulses, as shown in figure 11.2. The total high-level width during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be expressed as follows: TH = (data value in PWDRU and PWDRL + 4) * t/2 where t is the period of PWM clock input: 1/ (PWCR1 = 0, PWCR0 = 0), 2/ (PWCR1 = 0, PWCR0 = 1), 4/ (PWCR1 = 1, PWCR0 = 0), or 8/ (PWCR1 = 1, PWCR0 = 1). If the data value in PWDRU and PWDRL is from H'FFFC to H'FFFF, the PWM output stays high. When the data value is H'FC3C, TH is calculated as follows: TH = 64 * t/2 = 32 * t
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Section 11 10-Bit PWM
tf1
One conversion period tf2 tf3
tf4
tH1
tH2
tH3
tH4
TH = tH1 + tH2 + tH3 + tH4 tf1 = tf2 = tf3 = tf4
Figure 11.2 Waveform Output by 10-Bit PWM 11.4.2 PWM Operating States
Table 11.2 shows the PWM operating states. Table 11.2 PWM Operating States
Operating Mode
PWCR PWDRU PWDRL
Reset
Reset Reset Reset
Active
Functions Functions Functions
Sleep
Functions Functions Functions
Watch
Retained Retained Retained
Sub-active Sub-sleep
Retained Retained Retained Retained Retained Retained
Standby
Retained Retained Retained
Module Standby
Retained Retained Retained
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Section 12 A/D Converter
Section 12 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 12.1.
12.1
Features
* 10-bit resolution * Four input channels * Conversion time: at least 12.4 s per channel ( = 5 MHz operation)/6.2 s ( = 10 MHz operation)* * Sample and hold function * Conversion start method Software * Interrupt request An A/D conversion end interrupt request (ADI) can be generated * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) Note: * H8/38104 Group only.
ADCMS3AA_000020020900
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Section 12 A/D Converter
AMR
ADSR AN0 AN1 AN2 AN3 AVCC Multiplexer
Internal data bus
+
Comparator AVCC Reference voltage AVSS Control logic
AVSS
ADRRH ADRRL
Legend: AMR: ADSR: IRRAD: A/D mode register A/D start register A/D conversion end interrupt request flag
IRRAD
ADRRH, L: A/D result registers H and L
Figure 12.1 Block Diagram of A/D Converter
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Section 12 A/D Converter
12.2
Input/Output Pins
Table 12.1 shows the input pins used by the A/D converter. Table 12.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Abbreviation AVcc AVss AN0 AN1 AN2 AN3 I/O Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input pins
12.3
Register Descriptions
The A/D converter has the following registers. * A/D result registers H and L (ADRRH and ADRRL) * A/D mode register (AMR) * A/D start register (ADSR) 12.3.1 A/D Result Registers H and L (ADRRH and ADRRL)
ADRRH and ADRRL are 16-bit read-only registers that store the results of A/D conversion. The upper 8 bits of the data are stored in ADRRH, and the lower 2 bits in ADRRL. ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values during A/D conversion are undefined. After A/D conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial values of ADRRH and ADRRL are undefined.
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Section 12 A/D Converter
12.3.2
A/D Mode Register (AMR)
AMR sets the A/D conversion time and analog input pins.
Bit 7 Bit Name CKS Initial Value 0 R/W R/W Description Clock Select Sets the A/D conversion time. 0: Conversion time = 62 states 1: Conversion time = 31 states 6 5 4 3 2 1 0 CH3 CH2 CH1 CH0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W Reserved Only 0 can be written to this bit. Reserved These bits are always read as 1 and cannot be modified. Channel Select 3 to 0 Selects the analog input channel. 00XX: No channel selected 0100: AN0 0101: AN1 0110: AN2 0111: AN3 1XXX: Using prohibited The channel selection should be made while the ADSF bit is cleared to 0. Legend: X: Don't care.
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Section 12 A/D Converter
12.3.3
A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit 7 Bit Name ADSF Initial Value 0 R/W R/W Description When this bit is set to 1, A/D conversion is started. When conversion is completed, the converted data is set in ADRRH and ADRRL and at the same time this bit is cleared to 0. If this bit is written to 0, A/D conversion can be forcibly terminated. Reserved These bits are always read as 1 and cannot be modified.
6 to 0
All 1
12.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing the conversion time or analog input channel, in order to prevent incorrect operation, first clear the bit ADSF to 0 in ADSR. 12.4.1 1. 2. 3. 4. A/D Conversion
A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1, according to software. When A/D conversion is completed, the result is transferred to the A/D result register. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state.
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Section 12 A/D Converter
12.4.2
Operating States of A/D Converter
Table 12.2 shows the operating states of the A/D converter. Table 12.2 Operating States of A/D Converter
Operating Mode
AMR ADSR ADRRH ADRRL
Reset
Reset Reset Retained* Retained*
Active
Functions Functions Functions Functions
Sleep
Functions Functions Functions Functions
Watch
Retained Reset Retained Retained
Sub-active Sub-sleep Standby
Retained Reset Retained Retained Retained Reset Retained Retained Retained Reset Retained Retained
Module Standby
Retained Reset Retained Retained
Note:
*
Undefined in a power-on reset.
12.5
Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12.2 shows the operation timing. 1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is stored in ADRRH and ADRRL. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends.
2.
3. 4. 5. 6.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.3 and 12.4 show flowcharts of procedures for using the A/D converter.
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Interrupt (IRRAD) Set*
IENAD A/D conversion starts Set* Set*
ADSF
Channel 1 (AN1) operating state Idle
A/D conversion (1)
Idle Read conversion result A/D conversion result (1)
A/D conversion (2)
Idle Read conversion result A/D conversion result (2)
ADRRH ADRRL
Figure 12.2 Example of A/D Conversion Operation
Note: * indicates instruction execution by software.
Section 12 A/D Converter
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Section 12 A/D Converter
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0? Yes Read ADRRH/ADRRL data
Yes
Perform A/D conversion? No End
Figure 12.3 Flowchart of Procedure for Using A/D Converter (Polling by Software)
Start
Set A/D conversion speed and input channel
Enable A/D conversion end interrupt
Start A/D conversion
A/D conversion end interrupt generated? No
Yes
Clear IRRAD bit in IRR2 to 0
Read ADRRH/ADRRL data
Yes
Perform A/D conversion? No End
Figure 12.4 Flowchart of Procedure for Using A/D Converter (Interrupts Used)
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Section 12 A/D Converter
12.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.5). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 12.6). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 12.6). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 12 A/D Converter
Digital output
111 110 101 100 011 010 001 000 1 8
Ideal A/D conversion characteristic
Quantization error
2 8
3 8
4 8
5 8
6 8
7 FS 8 Analog input voltage
Figure 12.5 A/D Conversion Accuracy Definitions (1)
Digital output Full-scale error
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 12.6 A/D Conversion Accuracy Definitions (2)
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Section 12 A/D Converter
12.7
12.7.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. As a countermeasure, a large capacitance can be provided externally to the analog input pin. This will cause the actual input resistance to comprise only the internal input resistance of 10 k , allowing the signal source impedance to be ignored. This countermeasure has the disadvantage of creating a low-pass filter from the signal source impedance and capacitance, with the result that it may not be possible to follow analog signals having a large differential coefficient (e.g., 5 mV/s or greater) (see figure 12.7). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 12.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
This LSI Sensor output impedance to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k 20 pF
Figure 12.7 Example of Analog Input Circuit
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Section 12 A/D Converter
12.7.3 1. 2. 3. 4.
Additional Usage Notes
ADRRH and ADRRL should be read only when the ADSF bit in ADSR is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion. In active mode and sleep mode, the analog power supply current flows in the ladder resistance even when the A/D converter is on standby. Therefore, if the A/D converter is not used, it is recommended that AVcc be connected to the system power supply and the ADCKSTP bit be cleared to 0 in CKSTPR1.
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Section 13 LCD Controller/Driver
Section 13 LCD Controller/Driver
This LSI has an on-chip segment-type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel.
13.1
Features
* Display capacity
Duty Cycle Static 1/2 1/3 1/4 Internal Driver 25 SEG 25 SEG 25 SEG 25 SEG
* LCD RAM capacity 8 bits x 13 bytes (104 bits) * Word access to LCD RAM * The segment output pins can be used as ports. SEG24 to SEG1 pins can be used as ports in groups of four. * Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection). With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be used In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used * Choice of 11 frame frequencies * A or B waveform selectable by software * On-chip power supply split-resistance Removal of split-resistance can be controlled in software. Note that this capability is implemented in the H8/38104 Group only. * Display possible in operating modes other than standby mode * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.)
LCDSG02A_000020020900
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Section 13 LCD Controller/Driver
Figures 13.1(1) and 13.1(2) show a block diagram of the LCD controller/driver.
Vcc LCD drive power supply V1 V2 V3 Vss /2 to /256 w Common data latch Common driver COM1 COM4 SEG25 SEG24 SEG23 SEG22 SEG21 25-bit shift register Segment driver
Internal data bus
LPCR LCR LCR2 Display timing generator
LCD RAM 13 bytes SEG1 SEGn Legend: LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2
Figure 13.1(1) Block Diagram of LCD Controller/Driver (H8/3802 Group, H8/38004 Group, H8/38002S Group)
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Section 13 LCD Controller/Driver
Vcc V1 LCD drive power supply V2 V3 Vss /2 to /256 w Common data latch Common driver COM1 COM4 SEG25 SEG24 SEG23 SEG22 SEG21 25-bit shift register Segment driver
Internal data bus
LPCR LCR LCR2 Display timing generator
LCD RAM 13 bytes SEG1 SEGn Legend: LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2
Figure 13.1(2) Block Diagram of LCD Controller/Driver (H8/38104 Group)
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Section 13 LCD Controller/Driver
13.2
Input/Output Pins
Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration
Name Segment output pins Common output pins LCD power supply pins Abbreviation SEG25 to SEG1 I/O Output Function LCD segment drive pins All pins are multiplexed as port pins (setting programmable) COM4 to COM1 Output LCD common drive pins Pins can be used in parallel with static or 1/2 duty V1, V2, V3 -- Used when a bypass capacitor is connected externally, and when an external power supply circuit is used
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Section 13 LCD Controller/Driver
13.3
Register Descriptions
The LCD controller/driver has the following registers. * * * * LCD port control register (LPCR) LCD control register (LCR) LCD control register 2 (LCR2) LCD RAM LCD Port Control Register (LPCR)
13.3.1
LPCR selects the duty cycle, LCD driver, and pin functions.
Bit 7 6 5 Bit Name DTS1 DTS0 CMX Initial Value 0 0 0 R/W R/W R/W R/W Description Duty Cycle Select 1 and 0 Common Function Select The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. For details, see table 13.2. 4 3 2 1 0 -- SGS3 SGS2 SGS1 SGS0 -- 0 0 0 0 W R/W R/W R/W R/W Reserved Only 0 can be written to this bit. Segment Driver Select 3 to 0 Select the segment drivers to be used. For details, see table 13.3.
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Section 13 LCD Controller/Driver
Table 13.2 Duty Cycle and Common Function Selection
Bit 7: DTS1 0 Bit 6: DTS0 0 Bit 5: CMX 0 1 1 0 1 1/2 duty Duty Cycle Static Common Drivers Notes COM1 COM4 to COM1 COM2 to COM1 COM4 to COM1 Do not use COM4, COM3, and COM2 COM4, COM3, and COM2 output the same waveform as COM1 Do not use COM4 and COM3 COM4 outputs the same waveform as COM3, and COM2 outputs the same waveform as COM1 Do not use COM4 Do not use COM4 --
1
0 1
0 1 X
1/3 duty 1/4 duty
COM3 to COM1 COM4 to COM1 COM4 to COM1
Legend: X: Don't care
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Section 13 LCD Controller/Driver
Table 13.3 Segment Driver Selection
Function of Pins SEG25 to SEG1 Bit 3: Bit 2: Bit 1: Bit 0: SGS3 SGS2 SGS1 SGS0 SEG25 SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG21 SEG17 SEG13 SEG9 SEG5 SEG4 to SEG1
0
0
0
0 1
Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port
Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port
Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port
Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port
Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port
Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port
Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
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Section 13 LCD Controller/Driver
13.3.2
LCD Control Register (LCR)
LCR controls LCD drive power supply and display data, and selects the frame frequency.
Bit 7 6 Bit Name -- PSW Initial Value 1 0 R/W -- R/W Description Reserved This bit is always read as 1 and cannot be modified. LCD Drive Power Supply Control Can be used to disconnect the LCD drive power supply from Vcc when LCD display is not required in powerdown mode, or when an external power supply is used. When the ACT bit is cleared to 0, and also in standby mode, the LCD drive power supply is disconnected from Vcc regardless of the setting of this bit. 0: LCD drive power supply is disconnected from Vcc 1: LCD drive power supply is connected to Vcc 5 ACT 0 R/W Display Function Activate Specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless of the setting of the PSW bit. However, register contents are retained. 0: LCD controller/driver operation halted 1: LCD controller/driver operation enabled 4 DISP 0 R/W Display Data Control Specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. 0: Blank data is displayed 1: LCD RAM data is displayed 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Frame Frequency Select 3 to 0 Select the operating clock and the frame frequency. In subactive mode, watch mode, and subsleep mode, the system clock () is halted, and therefore display operations are not performed if one of the clocks from /2 to /256 is selected. If LCD display is required in these modes, W , W /2, or W /4 must be selected as the operating clock. For details, see table 13.4.
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Section 13 LCD Controller/Driver
Table 13.4 Frame Frequency Selection
Bit 3: CKS3 0 Bit 2: CKS2 X Bit 1: CKS1 0 1 1 0 0 1 1 0 1 Bit 0: CKS0 0 1 X 0 1 0 1 0 1 0 1 Frame Frequency*1 Operating Clock W W /2 W /4 /2 /4 /8 /16 /32 /64 /128 /256 = 2 MHz 128 Hz*2 64 Hz*2 32 Hz*2 -- 977 Hz 488 Hz 244 Hz 122 Hz 61 Hz 30.5 Hz --
3 = 250 kHz*
128 Hz*2 64 Hz*2 32 Hz*2 244 Hz 122 Hz 61 Hz 30.5 Hz -- -- -- --
Legend: X: Don't care Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 2. This is the frame frequency when W = 32.768 kHz. 3. This is the frame frequency in active (medium-speed, OSC/16) mode when = 2 MHz.
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Section 13 LCD Controller/Driver
13.3.3
LCD Control Register 2 (LCR2)
LCR2 controls switching between the A waveform and B waveform and removal of splitresistance. Note that removal of split-resistance control is only implemented on the H8/38104 Group.
Bit 7 Bit Name LCDAB Initial Value 0 R/W R/W Description A Waveform/B Waveform Switching Control Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform. 0: Drive using A waveform 1: Drive using B waveform 6, 5 4 -- -- All 1 -- All 0 -- W R/W Reserved These bits are always read as 1 and cannot be modified. Reserved This bit is always read as 0. 3 to 0* CDS3 CDS2 CDS1 CDS0 Removal of Split-Resistance Control These bits control whether the split-resistance is removed or connected. CDS3 = 0, CDS2 = CDS1 = CDS0 = 1: Split-resistance removed All other settings: Split-resistance connected Note: * Applies to H8/38104 Group only. On the H8/3802 Group, H8/38004 Group or H8/38002S Group, these bits are reserved like bit 4.
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Section 13 LCD Controller/Driver
13.4
13.4.1
Operation
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be determined. 1. Hardware Settings A. Using 1/2 duty When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2.
VCC V1 V2 V3 VSS
Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty B. Large-panel display As the impedance of the on-chip power supply split-resistance is large, it may not be suitable for driving a large panel. If the display lacks sharpness when using a large panel, refer to section 13.4.4, Boosting LCD Drive Power Supply. When static or 1/2 duty is selected, the common output drive capability can be increased. Set CMX to 1 when selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform is output from pins COM4 and COM3. C. LCD drive power supply setting With this LSI, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external power supply circuit. When an external power supply circuit is used for the LCD drive power supply, connect the external power supply to the V1 pin.
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Section 13 LCD Controller/Driver
2. Software Settings A. Duty selection Any of four duty cycles--static, 1/2 duty, 1/3 duty, or 1/4 duty--can be selected with bits DTS1 and DTS0. B. Segment selection The segment drivers to be used can be selected with bits SGS3 to SGS0. C. Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification. For the clock selection method in watch mode, subactive mode, and subsleep mode, see section 13.4.3, Operation in Power-Down Modes. D. A or B waveform selection Either the A or B waveform can be selected as the LCD waveform to be used by means of LCDAB. E. LCD drive power supply selection When an external power supply circuit is used, turn the LCD drive power supply off with the PSW bit.
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Section 13 LCD Controller/Driver
13.4.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7 H'F740 SEG2 Bit 6 SEG2 Bit 5 SEG2 Bit 4 SEG2 Bit 3 SEG1 Bit 2 SEG1 Bit 1 SEG1 Bit 0 SEG1
H'F74C COM4 COM3 COM2 COM1
SEG25 COM4
SEG25 COM3
SEG25 COM2
SEG25 COM1
Figure 13.3 LCD RAM Map (1/4 Duty)
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Section 13 LCD Controller/Driver
Bit 7 H'F740 Bit 6 SEG2 Bit 5 SEG2 Bit 4 SEG2 Bit 3 Bit 2 SEG1 Bit 1 SEG1 Bit 0 SEG1
H'F74C COM3 COM2 COM1
SEG25 COM3
SEG25 COM2
SEG25 COM1
Space not used for display
Figure 13.4 LCD RAM Map (1/3 Duty)
Bit 7 H'F740 SEG4 Bit 6 SEG4 Bit 5 SEG3 Bit 4 SEG3 Bit 3 SEG2 Bit 2 SEG2 Bit 1 SEG1 Bit 0 SEG1
Display space
H'F746
SEG25
SEG25
Space not used for display H'F74C COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1
Figure 13.5 LCD RAM Map (1/2 Duty)
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Section 13 LCD Controller/Driver
Bit 7 H'F740 SEG8 Bit 6 SEG7 Bit 5 SEG6 Bit 4 SEG5 Bit 3 SEG4 Bit 2 SEG3 Bit 1 SEG2 Bit 0 SEG1 Display space H'F743 SEG25
Space not used for display
H'F74C COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
Figure 13.6 LCD RAM Map (Static Mode)
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Section 13 LCD Controller/Driver
1 frame M M 1 frame
Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS (a) Waveform with 1/4 duty
Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS
COM1
COM1
COM2
COM2
COM3
COM3
COM4
SEGn
SEGn
V1 V2 V3 VSS (b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data V1 V2,V3 VSS V1 V2,V3 VSS V1 V2,V3 VSS (c) Waveform with 1/2 duty
Data V1 COM1 VSS V1 SEGn VSS
COM1
COM2
SEGn
(d) Waveform with static output
M: LCD alternation signal
Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)
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Section 13 LCD Controller/Driver
1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS (a) Waveform with 1/4 duty V1 V2 V3 VSS (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame 1 frame 1 frame 1 frame
COM1
COM1
COM2
COM2
COM3
COM3
COM4
SEGn
SEGn
1 frame
1 frame
1 frame
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data V1 V2,V3 VSS V1 V2,V3 VSS V1 V2,V3 VSS (c) Waveform with 1/2 duty
Data V1 COM1 VSS V1 SEGn VSS
COM1
COM2
SEGn
(d) Waveform with static output M: LCD alternation signal
Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)
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Section 13 LCD Controller/Driver
Table 13.5 Output Levels
Data M Static 1/2 duty 1/3 duty 1/4 duty M: Common output Segment output Common output Segment output Common output Segment output Common output Segment output LCD alternation signal 0 0 V1 V1 V2, V3 V1 V3 V2 V3 V2 0 1 VSS VSS V2, V3 VSS V2 V3 V2 V3 1 0 V1 VSS V1 VSS V1 VSS V1 VSS 1 1 VSS V1 VSS V1 VSS V1 VSS V1
13.4.3
Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 13.6. In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless W, W/2, or W/4 has been selected by bits CKS3 to CKS0, the clock will not be supplied and display will halt. Since there is a possibility that a direct current will be applied to the LCD panel in this case, it is essential to ensure that W, W/2, or W/4 is selected. In active (medium-speed) mode, the system clock is switched, and therefore bits CKS3 to CKS0 must be modified to ensure that the frame frequency does not change.
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Section 13 LCD Controller/Driver
Table 13.6 Power-Down Modes and Display Operation
Mode Clock w Reset Runs Runs Active Runs Runs Stops Sleep Runs Runs Stops Watch Stops Runs Stops Subactive Stops Runs Stops Subsleep Stops Runs Stops Module Standby Standby Stops Stops *1 Stops*4 Stops*4 Stops Stops
Display ACT = 0 Stops operation ACT = 1 Stops
Stops*2
3 3 3 2 Functions Functions Functions* Functions* Functions* Stops*
Notes: 1. The subclock oscillator does not stop, but clock supply is halted. 2. The LCD drive power supply is turned off regardless of the setting of the PSW bit. 3. Display operation is performed only if W , W /2, or W /4 is selected as the operating clock. 4. The clock supplied to the LCD stops.
13.4.4
Boosting LCD Drive Power Supply
When the on-chip power supply capacity is insufficient for the LCD panel drivability, the powersupply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 F to pins V1 to V3, as shown in figure 13.9, or by adding a split-resistor externally.
VCC V1
R
R This LSI V2 R V3 R VSS
R = several k to several M
C = 0.1 to 0.3 F
Figure 13.9 Connection of External Split-Resistance
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Section 13 LCD Controller/Driver
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
This LSI can include a power-on reset circuit. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits. This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. Even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. Thus, system stability can be improved. If the power supply voltage falls more, the reset state is automatically entered. If the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. Figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit. Note: * The voltage maintained in standby mode is the same as the RAM data maintenance voltage (VRAM). See section 17.6.2, DC Characteristics, for information on maintenance voltage electrical characteristics.
14.1
Features
* Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. * Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply rise/drop detection voltages and a detection voltage reference voltage may be input from an external source, allowing the detection level to be set freely by the user.
LVI0000A_000020030300
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
CK R
OVF PSS R
RES
Noise canceler
Q S Power-on reset circuit
Internal reset signal
Noise canceler
External power supply extD External ladder resistor extU Vref
Vcc
Ladder resistor
Vreset
+
- -
Vint
LVDRES Interrupt control circuit LVDSR
+
LVDINT
Interrupt request External reference voltage generator On-chip reference voltage generator
Low-voltage detection circuit Legend: PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: extD: extU: Vref: Prescaler S Low-voltage-detection control register Low-voltage-detection status register Low-voltage-detection reset signal Low-voltage-detection interrupt signal Reset detection voltage Power-supply fall/rise detection voltage Power supply drop detection voltage input pin Power supply rise detection voltage input pin Reference voltage input pin
Figure 14.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
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Internal data bus
LVDCR
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
14.2
Register Descriptions
The low-voltage detection circuit has the following registers. * Low-voltage-detection control register (LVDCR) * Low-voltage-detection status register (LVDSR) * Low-voltage detection counter (LVDCNT) 14.2.1 Low-Voltage Detection Control Register (LVDCR)
LVDCR is used to control whether or not the low-voltage detection circuit is used, settings for external input of power supply drop and rise detection voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the low-voltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power supply voltage drops or rises. Table 14.1 shows the relationship between LVDCR settings and function selections. Refer to table 14.1 when making settings to LVDCR.
Bit 7 Bit Name LVDE Initial Value 0* R/W R/W Description LVD Enable 0: Low-voltage detection circuit not used (standby status) 1: Low-voltage detection circuit used 6 5 VINTDSEL 0 0 R/W R/W This bit is reserved. Power Supply Drop (LVDD) Detection Level External Input Select 0: LVDD detection level generated by on-chip ladder resistor 1: LVDD detection level input to extD pin 4 VINTUSEL 0 R/W Power Supply Rise (LVDU) Detection Level External Input Select 0: LVDU detection level generated by on-chip ladder resistor 1: LVDU detection level input to extU pin
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only) Initial Value 0*
Bit 3
Bit Name LVDSEL
R/W R/W
Description LVDR Detection Level Select 0: Reset detection voltage 2.3 V (typ.) 1: Reset detection voltage 3.3 V (typ.) Select 2.3 V (typical) reset if voltage rise and drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset.
2
LVDRE
0*
R/W
LVDR Enable 0: LVDR resets disabled 1: LVDR resets enabled
1
LVDDE
0
R/W
Voltage Drop Interrupt Enable 0: Voltage drop interrupt requests disabled 1: Voltage drop interrupt requests enabled
0
LVDUE
0
R/W
Voltage Rise Interrupt Enable 0: Voltage rise interrupt requests disabled 1: Voltage rise interrupt requests enabled
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by power-on resets and watchdog timer resets.
Table 14.1 LVDCR Settings and Select Functions
LVDCR Settings Select Functions
Low-VoltageDetection Falling Interrupt Low-VoltageDetection Rising Interrupt
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On Reset
LVDR
0 1 1 1 1 Legend:
* 1 0 0 0
* 1 0 0 1 * means invalid.
* 0 1 1 1
* 0 0 1 1
O O O O O
O O
O O O
O O
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
14.2.2
Low-Voltage Detection Status Register (LVDSR)
LVDSR is used to control external input selection, indicates when the reference voltage is stable, and indicates if the power supply voltage goes below or above a specified range.
Bit 7 Bit Name OVF Initial Value 0* R/W R/W Description LVD Reference Voltage Stabilized Flag Setting condition: When the low-voltage detection counter (LVDCNT) overflows Clearing condition: When 0 is written after reading 1 6 to 4 3 0 R/W R/W These are read/write enabled reserved bits. Reference Voltage External Input Select 0: The on-chip circuit is used to generate the reference voltage 1: The reference voltage is input to the Vref pin from an external source 2 1 LVDDF 0 0* R/W R/W This bit is reserved. It is always read as 0 and cannot be written to. LVD Power Supply Voltage Drop Flag Setting condition: When the power supply voltage drops below Vint(D) Clearing condition: When 0 is written after reading 1 0 LVDUF 0* R/W LVD Power Supply Voltage Rise Flag Setting condition: When the power supply voltage drops below Vint(D) while the LVDUE bit in LVDCR is set to 1, and it rises above Vint(U) before dropping below Vreset1 Clearing condition: When 0 is written after reading 1 Note: * These bits are initialized by resets trigged by LVDR. VREFSEL 0
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
14.2.3
Low-Voltage Detection Counter (LVDCNT)
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The counter increments using /4 as the clock source until it overflows by switching from H'FF to H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by until the counter has overflowed. The initial value of LVDCNT is H'00.
14.3
14.3.1
Operation
Power-On Reset Circuit
Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the pin is gradually charged via the on-chip pull-up resistor (typ. 100 k). Since the state of the pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states. When the level on the pin reaches the specified value, the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler S has counted 131,072 clock () cycles. The noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the pin. To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles within the specified time. The maximum time required for the power supply to rise and settle after power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to pin (C ). If tPWON means the time required to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula.
SER
tPWON (ms) 80 * C
(F) 10/fOSC (MHz) 0.22 F, and fOSC = 10 in 2-MHz to 10-MHz operation)
SER
(tPWON 3000 ms, C
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on pin is removed. To remove charge on the pin, it is recommended that the diode the should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.
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SER
SER SER
SER
SER
SER
SER
SER
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
tPWON Vcc Vpor Vss
Vss PSS-reset signal OVF Internal reset signal
131,072 cycles PSS counter starts Reset released
Figure 14.2 Operational Timing of Power-On Reset Circuit 14.3.2 Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit: Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 150 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of LVDCNT, then set the LVDRE bit in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur. When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR signal to 0, and resets the prescaler S. The low-voltage detection reset state clears the remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock () cycles, and then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in LVDCR are not initialized. Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that point, the low-voltage detection reset may not occur. If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
SERDVL
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
VCC
Vreset
VLVDRmin VSS
PSS-reset signal
OVF
Internal reset signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of LVDNT, then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits because incorrect operation may occur. When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the external EEPROM, etc, and a transition must be made to standby mode, watch mode, or subsleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above signal to 1. If the LVDUE bit is 1 at Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the
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TNIDVL
TNIDVL
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed.
Vcc
Vint (U) Vint (D) Vreset1 VSS
LVDDE
LVDDF
LVDUE LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 14.4 Operational Timing of LVDI Circuit The reference voltage, power supply voltage drop detection level, and power supply voltage rise detection level can be input to the LSI from external sources via the Vref, extD, and extU pins. Figure 14.5 shows the operational timing using input from the Vref, extD, and extU pins. First, make sure that the voltages input to pins extD and extU are set to higher levels than the interrupt detection voltage Vexd. After initial settings are made, a power supply drop interrupt is generated if the extD input voltage drops below Vexd. After a power supply drop interrupt is generated, if the external power supply voltage rises and the extU input voltage rises higher than Vexd, a power supply rise interrupt is generated. As with the on-chip circuit, the above function should be used in conjunction with LVDR (Vreset1) when the LVDI function is used.
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
External power supply voltage extD input voltage extU input voltage (1) (2) (3) Vexd
(4) Vreset1 VSS
LVDINTD
LVDDF
LVDINTU
LVDUF
IRQ0 interrupt generated
IRQ0 interrupt generated
Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit (Using Pins Vref, extD, and extU)
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU.
LVDCR R1 R2
On-chip ladder resistor External power supply voltage R1 = 517 k R2 = 33 k R3 = 450 k extU extD
+ -
LVDRES
D1 U1
D2 U2
+ -
LVDINT
Interrupt controller
LVDSR Interrupt request
Vref
External reference voltage 1.3 V
On-chip reference voltage generator
Setting conditions: * Vref = 1.3 V external input (This Vref value results in a Vreset value of 2.5 V.) * Power supply drop detection voltage input of 2.7 V from extD * Power supply rise detection voltage input of 2.9 V from extU * 1 M variable resistor connected externally
Figure 14.6 LVD Function Usage Example Employing Pins Vref, extD, and extU Below is an explanation of the method for calculating the external resistor values when using the Vref, extD, and extU pins for input of reference and detection voltages from sources external to the LSI. Procedure: 1. First, determine the overall resistance value, R. The current consumed by the resistor is determined by the value of R. A lower R will result in a greater current flow, and a higher R will result in a reduced current flow. The value of R is dependent on the configuration of the system in which the LSI is installed. 2. Determine the power supply drop detection voltage (Vint(D)) and the power supply rise detection voltage (Vint(U)). 3. Using a resistance value calculation table like the one shown below, plug in values for R, Vreset1, Vint(D), and Vint(U) to calculate the values of Vref, R1, R2, and R3.
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Resistance Value Calculation Table
Ex. No 1 2 3 4 Vref (V) 1.30 1.41 1.57 2.09 R (k) 1000 1000 1000 1000 Vreset1 2.5 2.7 3 4 Vint(D) 2.7 2.9 3.2 4.5 Vint(U) 2.9 3 3.5 4.7 R1 (k) 517 514 511 536 R2 (k) 33 16 42 20 R3 (k) 450 470 447 444
4. Using an error calculation table like the one shown below, plug in values for R1, R2, R3, and Vref to calculate the deviation of Vreset1, Vint(D), and Vint(U). Make sure to double check the maximum and minimum values for each value. Error Calculation Table
Resistance Value Error (%) 5 R1+Err, R2/R3-Err
Vref (V) 1.3
R1 (k) 517
R2 (k) 33
R3 (k) 450
Comparator Vreset1 Error (V) (V) 0.1 0 -0.1 2.59 2.49 2.39 2.59 2.49 2.39 2.59 2.49 2.39 2.59 2.49 2.39 2.59 2.49 2.39
Vint(D) (V) 2.94 2.84 2.74 2.66 2.56 2.46 2.79 2.69 2.59 2.93 2.83 2.73 2.67 2.57 2.47
Vint(U) (V) 3.15 3.05 2.95 2.85 2.75 2.65 2.99 2.89 2.79 3.16 3.06 2.96 2.84 2.74 2.64
R1-Err, R2/R3+Err
0.1 0 -0.1
R1/R2/R3 No Err
0.1 0 -0.1
R1/R2+Err, R3-Err
0.1 0 -0.1
R1/R2-Err, R3+Err
0.1 0 -0.1
Rev. 6.00 Mar 15, 2005 page 360 of 502 REJ09B0024-0600
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 14.7 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2. Wait for 150 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of LVDNT. Then, clear the LVDDF and LVDUF bits in LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as required. 3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 14.7 Timing for Operation/Release of Low-Voltage Detection Circuit
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
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Section 15 Power Supply Circuit (H8/38104 Group Only)
Section 15 Power Supply Circuit (H8/38104 Group Only)
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the same as the external voltage. It is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit.
15.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 F between CVCC and VSS, as shown in figure 15.1. The internal step-down circuit is made effective simply by adding this external circuit. In the external circuit interface, the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the VCC level is the reference for the high level, and the VSS level is that for the low level. The A/D converter analog power supply is not affected by the internal step-down circuit.
VCC VCC = 2.7 to 5.5 V
Step-down circuit
CVCC
Internal logic
Internal power supply VSS
Stabilization capacitance (approx. 0.1 F)
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used
PSCKT00A_000020020200
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Section 15 Power Supply Circuit (H8/38104 Group Only)
15.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
VCC VCC = 2.7 to 3.6 V
Step-down circuit
CVCC
Internal logic
Internal power supply VSS
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
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Section 16 List of Registers
Section 16 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 16 List of Registers
16.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Register Name Flash memory control register 1 Flash memory control register 2 Flash memory power control register Erase block register Flash memory enable register Low-voltage detection control register*4 Low-voltage detection status register*4 Event counter PWM compare register H Event counter PWM compare register L Abbreviation FLMCR1 FLMCR2 FLPWCR EBR FENR LVDCR LVDSR Module Bit No Address Name 8 8 8 8 8 8 8 H'F020 H'F021 H'F022 H'F023 H'F02B H'FF86 H'FF87 H'FF8C H'FF8D H'FF8E H'FF8F H'FF90 H'FF91 H'FF92 H'FF94 H'FF95 H'FF96 H'FF97 H'FFA8 H'FFA9 H'FFAA ROM ROM ROM ROM ROM LVD LVD AEC*1 AEC*1 AEC*1 AEC*1 Interrupts SCI3 AEC*1 AEC *1 AEC*1 AEC* AEC*1 SCI3 SCI3 SCI3
1
Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3
ECPWCRH 8 ECPWCRL 8
Event counter PWM data register ECPWDRH 8 H Event counter PWM data register ECPWDRL 8 L Wakeup edge select register Serial port control register Input pin edge select register Event counter control register Event counter control/status register Event counter H Event counter L Serial mode register Bit rate register Serial control register 3 WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR BRR SCR3 8 8 8 8 8 8 8 8 8 8
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Section 16 List of Registers Abbreviation TDR SSR RDR TMA TCA TCSRW TCW TCRF TCSRF TCFH TCFL OCRFH OCRFL LPCR LCR LCR2 *4 LVDCNT ADRRH ADRRL AMR ADSR PMR2 PMR3 PMR5 PWCR2 PWDRU2 PWDRL2 PWCR1 PWDRU1 PWDRL1 PDR3 PDR4 Module Bit No Address Name 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFAB H'FFAC H'FFAD H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC9 H'FFCA H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD6 H'FFD7 SCI3 SCI3 SCI3 Timer A Timer A WDT*2 WDT*2 Timer F Timer F Timer F Timer F Timer F Timer F LCD*3 LCD*3 LCD*3 LVD Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Transmit data register Serial status register Receive data register Timer mode register A Timer counter A Timer control/status register W Timer counter W Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL LCD port control register LCD control register LCD control register 2 Low-voltage detection counter A/D result register H A/D result register L A/D mode register A/D start register Port mode register 2 Port mode register 3 Port mode register 5 PWM2 control register PWM2 data register U PWM2 data register L PWM1 control register PWM1 data register U PWM1 data register L Port data register 3 Port data register 4
A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 I/O port I/O port I/O port 10-bit PWM 10-bit PWM 10-bit PWM 10-bit PWM 10-bit PWM 10-bit PWM I/O port I/O port 8 8 8 8 8 8 8 8 8 8 8
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Section 16 List of Registers Abbreviation PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PUCR3 PUCR5 PUCR6 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PMR9 PCRA PMRB SYSCR1 SYSCR2 IEGR IENR1 IENR2 OSCCR IRR1 IRR2 TMW Module Bit No Address Name 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFE1 H'FFE2 H'FFE3 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFEE H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port SYSTEM SYSTEM Interrupts Interrupts Interrupts CPG Interrupts Interrupts WDT*2 Interrupts SYSTEM SYSTEM Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Port data register 5 Port data register 6 Port data register 7 Port data register 8 Port data register 9 Port data register A Port data register B Port pull-up control register 3 Port pull-up control register 5 Port pull-up control register 6 Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port mode register 9 Port control register A Port mode register B System control register 1 System control register 2 IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Oscillator control register*4 Interrupt request register 1 Interrupt request register 2 Timer mode register W *4
Wakeup interrupt request register IWPR Clock stop register 1 Clock stop register 2
CKSTPR1 8 CKSTPR2 8
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Section 16 List of Registers Notes: 1. 2. 3. 4. AEC: Asynchronous event counter WDT: Watchdog timer LCD: LCD controller/driver H8/38104 Group only
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Section 16 List of Registers
16.2
Register Bits
Register bit names of the on-chip peripheral modules are described below.
Register Abbreviation Bit 7 FLMCR1 FLMCR2 FLPWCR EBR FENR LVDCR*4
4 LVDSR*
Bit 6 SWE -- -- -- -- -- --
Bit 5 ESU -- -- -- --
Bit 4 PSU -- -- EB4 --
Bit 3 EV -- -- EB3 --
Bit 2 PV -- -- EB2 -- LVDRE
Bit 1 E -- -- EB1 -- LVDDE LVDDF
Bit 0 P -- -- EB0 -- LVDUE LVDUF
Module Name ROM
-- FLER PDWND -- FLSHE LVDE OVF
VINTDSEL VINTUSEL LVDSL
--
--
VREFSEL --
Lowvoltage detect circuit
1
ECPWCRH ECPWCRL ECPWDRH ECPWDRL WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR BRR SCR3 TDR SSR RDR TMA TCA TCSRW TCW
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 AEC * ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts -- -- SPC32 -- SCINV3 SCINV2 AIEGS0 PWCK1 CUEL ECH2 ECL2 MP BRR2 TEIE TDR2 TEND RDR2 TMA2 TCA2 WDON TCW2 -- -- SCI3 AEC*1
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 ACKH1 OVH ECH7 ECL7 COM BRR7 TIE TDR7 TDRE RDR7 -- TCA7 B6WI TCW7 ACKH0 OVL ECH6 ECL6 CHR BRR6 RIE TDR6 RDRF RDR6 -- TCA6 TCWE TCW6 ACKL1 -- ECH5 ECL5 PE BRR5 TE TDR5 OER RDR5 -- TCA5 B4WI TCW5 ACKL0 CH2 ECH4 ECL4 PM BRR4 RE TDR4 FER RDR4 -- TCA4 PWCK2 CUEH ECH3 ECL3 STOP BRR3 MPIE TDR3 PER RDR3 TMA3 TCA3
ECPWME -- PWCK0 CRCH ECH1 ECL1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 TMA1 TCA1 BOWI TCW1 -- CRCL ECH0 ECL0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 TMA0 TCA0 WRST TCW0
SCI3
Timer A
TCSRWE B2WI TCW4 TCW3
WDT*2
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Section 16 List of Registers
Register Abbreviation Bit 7 TCRF TCSRF TCFH TCFL OCRFH OCRFL LPCR LCR LCR2 LVDCNT *4 TOLH OVFH TCFH7 TCFL7 Module Name Timer F
Bit 6 CKSH2 CMFH TCFH6 TCFL6
Bit 5 CKSH1 OVIEH TCFH5 TCFL5
Bit 4 CKSH0 CCLRH TCFH4 TCFL4
Bit 3 TOLL OVFL TCFH3 TCFL3
Bit 2 CKSL2 CMFL TCFH2 TCFL2
Bit 1 CKSL1 OVIEL TCFH1 TCFL1
Bit 0 CKSL0 CCLRL TCFH0 TCFL0
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 DTS1 -- LCDAB CNT7 DTS0 PSW -- CNT6 CMX ACT -- CNT5 -- DISP -- CNT4 SGS3 CKS3 CDS3*4 CNT3 SGS2 CKS2 CDS2*4 CNT2 SGS1 CKS1 CDS1*4 CNT1 SGS0 CKS0 CDS0*4 CNT0 Lowvoltage detect circuit A/D converter LCD*3
ADRRH ADRRL AMR ADSR PMR2 PMR3 PMR5 PWCR2 PWDRU2 PWDRL2 PWCR1 PWDRU1 PWDRL1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB
ADR9 ADR1 CKS ADSF -- AEVL WKP7 -- --
ADR8 ADR0 -- -- -- AEVH WKP6 -- --
ADR7 -- -- -- POF1 -- WKP5 -- --
ADR6 -- -- -- -- -- WKP4 -- --
ADR5 -- CH3 -- -- -- WKP3 -- --
ADR4 -- CH2 -- WDCKS TMOFH WKP2
ADR3 -- CH1 -- -- TMOFL WKP1
ADR2 -- CH0 -- IRQ0 -- WKP0
I/O port
PWCR22*4 PWCR21 PWCR20 10-bit
--
PWDRU21 PWDRU20
PWM
PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20
-- --
-- --
-- --
-- --
-- --
PWCR12*4 PWCR11 PWCR10
--
PWDRU11 PWDRU10
PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10
P37 -- P57 P67 P77 -- -- -- --
P36 -- P56 P66 P76 -- -- -- --
P35 -- P55 P65 P75 -- P95 -- --
P34 -- P54 P64 P74 -- P94 -- --
P33 P43 P53 P63 P73 -- P93 PA3 PB3
P32 P42 P52 P62 P72 -- P92 PA2 PB2
P31 P41 P51 P61 P71 -- P91 PA1 PB1
-- P40 P50 P60 P70 P80 P90 PA0 PB0
I/O port
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Section 16 List of Registers
Register Abbreviation Bit 7 PUCR3 PUCR5 PUCR6 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PMR9 PCRA PMRB SYSCR1 SYSCR2 IEGR IENR1 IENR2 OSCCR*4 IRR1 IRR2 TMW *4 IWPR CKSTPR1 CKSTPR2 Module Name I/O port
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 -- PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 PCR37 -- PCR57 PCR67 PCR77 -- -- -- -- SSBY -- -- IENTA IENDT PCR36 -- PCR56 PCR66 PCR76 -- -- -- -- STS2 -- -- -- IENAD PCR35 -- PCR55 PCR65 PCR75 -- -- -- -- STS1 -- -- IENWP -- -- -- -- -- IWPF5 PCR34 -- PCR54 PCR64 PCR74 -- -- -- -- STS0 NESEL -- -- -- -- -- -- -- IWPF4 PCR33 -- PCR53 PCR63 PCR73 -- PIOFF PCRA3 IRQ1 LSON DTON -- -- IENTFH -- -- IRRTFH CKS3 IWPF3 PCR32 PCR42 PCR52 PCR62 PCR72 -- -- PCRA2 -- -- MSON -- IENEC2 IENTFL PCR31 PCR41 PCR51 PCR61 PCR71 -- PWM2 PCRA1 -- MA1 SA1 IEG1 IEN1 -- -- PCR40 PCR50 PCR60 PCR70 PCR80 PWM1 PCRA0 -- MA0 SA0 IEG0 IEN0 IENEC -- IRRI0 IRREC CKS0 IWPF0
SYSTEM
Interrupts
SUBSTP -- IRRTA IRRDT -- IWPF7 -- -- IRRAD -- IWPF6 --
IRQAECF OSCF IRREC2 IRRTFL CKS2 IWPF2 IRRI1 -- CKS1 IWPF1
CPG Interrupts
WDT*2 Interrupts
S32CKSTP ADCKSTP --
TFCKSTP --
TACKSTP SYSTEM
LVDCKSTP -- *4
--
PW2CKSTP
AECKSTP WDCKSTPPW1CKSTP LDCKSTP
Notes: 1. 2. 3. 4.
AEC: Asynchronous event counter WDT: Watchdog timer LCD: LCD controller/driver H8/38104 Group only
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Section 16 List of Registers
16.3
Register States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized *4 Active -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- Watch Initialized -- -- Initialized -- -- -- Subactive Subsleep Standby Initialized -- -- Initialized -- -- -- Initialized -- -- Initialized -- -- -- Initialized -- -- Initialized -- -- -- Lowvoltage detect circuit AEC*
1
Register Abbreviation FLMCR1 FLMCR2 FLPWCR EBR FENR LVDCR*4 LVDSR
Module ROM
ECPWCRH ECPWCRL ECPWDRH ECPWDRL WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR BRR SCR3 TDR SSR RDR TMA TCA TCSRW TCW
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- --
Interrupts SCI3 AEC*1
SCI3
Timer A WDT*2
Rev. 6.00 Mar 15, 2005 page 373 of 502 REJ09B0024-0600
Section 16 List of Registers
Register Abbreviation TCRF TCSRF TCFH TCFL OCRFH OCRFL LPCR LCR LCR2 LVDCNT*4
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- --
Watch -- -- -- -- -- -- -- -- -- --
Subactive Subsleep Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module Timer F
LCD*
3
Lowvoltage detect circuit A/D converter
ADRRH ADRRL AMR ADSR PMR2 PMR3 PMR5 PWCR2 PWDRU2 PWDRL2 PWCR1 PWDRU1 PWDRL1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB
-- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- Initialized -- -- -- -- -- -- -- -- -- -- --
-- -- -- Initialized -- -- -- -- -- -- -- -- -- -- --
-- -- -- Initialized -- -- -- -- -- -- -- -- -- -- --
-- -- -- Initialized -- -- -- -- -- -- -- -- -- -- --
I/O port
10-bit PWM
I/O port
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
Rev. 6.00 Mar 15, 2005 page 374 of 502 REJ09B0024-0600
Section 16 List of Registers
Register Abbreviation PUCR3 PUCR5 PUCR6 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PMR9 PCRA PMRB SYSCR1 SYSCR2 IEGR IENR1 IENR2 OSCCR*4 IRR1 IRR2 TMW * IWPR CKSTPR1 CKSTPR2
4
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Watch
Subactive Subsleep Standby
Module I/O port
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
SYSTEM
Interrupts
CPG Interrupts
2 WDT*
Interrupts SYSTEM
Notes: is not initialized 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer 3. LCD: LCD controller/driver 4. H8/38104 Group only
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Section 16 List of Registers
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Section 17 Electrical Characteristics
Section 17 Electrical Characteristics
17.1 Absolute Maximum Ratings of H8/3802 Group (ZTAT Version, Mask ROM Version)
Table 17.1 lists the absolute maximum ratings. Table 17.1 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Programming voltage Input voltage Other than port B and IRQAEC Port B IRQAEC Port 9 pin voltage Operating temperature Symbol VCC AVCC VPP Vin AVin HVin VP9 Topr Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +13.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.3 -0.3 to +7.3 Regular specifications: -20 to +75 Wide-range temperature specifications: -40 to +85 Storage temperature Note: * Tstg -55 to +125 C Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. Unit V V V V V V V C Note *
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Section 17 Electrical Characteristics
17.2
Electrical Characteristics of H8/3802 Group (ZTAT Version, Mask ROM Version)
Power Supply Voltage and Operating Ranges
17.2.1
Power Supply Voltage and Oscillation Frequency Range
16.0
38.4
fosc (MHz)
fW (kHz)
1.8 2.7 4.5 5.5 VCC (V)
32.768
10.0
4.0 2.0 1.8 3.0 4.5 5.5 VCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode Note 1: The fosc values are those when a resonator is used; when an external clock is used, the minimum value of fosc is 1 MHz.
* All operating modes Note 2: When a resonator is used, hold Vcc at 2.2 V to 5.5 V from power-on until the oscillation stabilization time has elapsed.
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Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
8.0 19.2
(MHz)
5.0
16.384
2.0 1.0 (0.5)
SUB (kHz)
9.6 1.8 2.7 4.5 5.5 VCC (V) 8.192
* Active (high-speed) mode * Sleep (high-speed) mode (except CPU) Note 1: The values in parentheses is the minimum operating frequency when an external clock is input. When using a resonator, the minimum operating frequency () is 1 MHz.
4.8 4.096
1.8
3.6
5.5 VCC (V)
* Subactive mode 1000 * Subsleep mode (except CPU) * Watch mode (except CPU)
(kHz)
625
250 15.625 (7.8125) 1.8 2.7 4.5 5.5 VCC (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter) Note 2: The values in parentheses is the minimum operating frequency when an external clock is input. When using a resonator, the minimum operating frequency () is 15.625 kHz.
Rev. 6.00 Mar 15, 2005 page 379 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range
5.0
(MHz) (kHz)
1000
1.0 (0.5) 1.8 2.7 4.5 5.5 AVCC (V)
625 500 1.8 2.7 4.5 5.5 AVCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Active (medium-speed) mode * Sleep (medium-speed) mode
Note: When AVcc = 1.8 V to 2.7 V, the operating range is limited to = 1.0 MHz when using a resonator and is = 0.5 MHz to 1.0 MHz when using an external clock.
Rev. 6.00 Mar 15, 2005 page 380 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.2.2
DC Characteristics
Table 17.2 lists the DC characteristics. Table 17.2 DC Characteristics (1) VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Values Item Symbol Applicable Pins Test Condition Min Typ Max VCC + 0.3 Unit V Notes
Note: Connect the TEST pin to VSS.
,1QRI 0QRI 7PKW 0PKW SER
to , AEVL, AEVH, SCK32 RXD32 OSC1 X1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 PB0 to PB3 IRQAEC
Input high VIH voltage
,
VCC = 4.0 V to 5.5 V VCC x 0.8 --
,
Other than above
VCC x 0.9 -- VCC x 0.8 -- VCC x 0.9 --
VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V V
VCC = 4.0 V to 5.5 V VCC x 0.7 -- Other than above VCC = 4.0 V to 5.5 V VCC x 0.8 -- Other than above VCC = 1.8 V to 5.5 V VCC x 0.9 -- VCC = 4.0 V to 5.5 V VCC x 0.7 --
Other than above
VCC x 0.8 --
VCC + 0.3
VCC = 4.0 V to 5.5 V VCC x 0.7 -- Other than above VCC x 0.8 -- VCC x 0.9 -- VCC = 4.0 V to 5.5 V VCC x 0.8 -- Other than above
AVCC + 0.3 AVCC + 0.3 7.3 7.3
V
V
Rev. 6.00 Mar 15, 2005 page 381 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (2) VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Values Item Input low voltage Symbol VIL Applicable Pins Test Condition Min Typ -- Max VCC x 0.2 Unit V Notes
Output high voltage
VOH
Rev. 6.00 Mar 15, 2005 page 382 of 502 REJ09B0024-0600
,1QRI 0QRI 7PKW 0PKW SER
to , IRQAEC, AEVL, AEVH, SCK32 RXD32 OSC1 X1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3, PB0 to PB3 P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3
,
VCC = 4.0 V to 5.5 V - 0.3
,
Other than above
- 0.3
-- -- -- -- -- -- --
VCC x 0.1 VCC x 0.3 VCC x 0.2 VCC x 0.2 VCC x 0.1 VCC x 0.1 VCC x 0.3 V V V V
VCC = 4.0 V to 5.5 V - 0.3 Other than above - 0.3
VCC = 4.0 V to 5.5 V - 0.3 Other than above - 0.3
VCC = 1.8 V to 5.5 V - 0.3 VCC = 4.0 V to 5.5 V - 0.3
Other than above
- 0.3
--
VCC x 0.2
VCC = 4.0 V to 5.5 V VCC - 1.0 -- -IOH = 1.0 mA VCC = 4.0 V to 5.5 V VCC - 0.5 -- -IOH = 0.5 mA -IOH = 0.1 mA VCC - 0.3 --
--
V
--
--
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (3) VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Values Item Symbol Applicable Pins P40 to P42 Test Condition Min Typ -- Max 0.6 Unit V Notes
Output low VOL voltage
VCC = 4.0 V to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA -- --
-- --
0.5 0.5
P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 P31 to P37
IOL = 0.4 mA
VCC = 4.0 V to 5.5 V -- IOL = 10 mA VCC = 4.0 V to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA --
--
1.5
--
0.6
-- --
0.5 0.5 *5
P90 to P92
VCC = 2.2 V to 5.5 V -- IOL = 25 mA IOL = 15 mA IOL = 10 mA
*6 -- -- -- -- -- 0.5 20.0 1.0 1.0 A A *2 *1
P93 to P95
IOL = 10 mA
SER
Input/ output leakage current
| IIL |
, P43
VIN = 0.5 V to VCC - -- 0.5 V --
OSC1, X1, P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, IRQAEC, PA0 to PA3, P90 to P95 PB0 to PB3
VIN = 0.5 V to VCC - -- 0.5 V
VIN = 0.5 V to AVCC -- - 0.5 V
--
1.0
Rev. 6.00 Mar 15, 2005 page 383 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (4) VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Values Item Pull-up MOS current Symbol -Ip Applicable Pins P31 to P37, P50 to P57, P60 to P67 Test Condition VCC = 5.0 V, VIN = 0.0 V VCC = 2.7 V, VIN = 0.0 V Min 50.0 -- -- Typ -- 35.0 -- Max 300.0 -- 15.0 pF Unit A Reference value Notes
IRQAEC
P43
PB0 to PB3 Active IOPE1 mode current consumption IOPE2 VCC
VCC
ISLEEP Sleep mode current consumption
VCC
Rev. 6.00 Mar 15, 2005 page 384 of 502 REJ09B0024-0600
SER
Input capacitance
Cin
f = 1 MHz, All input pins VIN = 0.0 V, except power supply, , P43, Ta = 25C IRQAEC, PB0 to PB3 pins
-- -- -- -- -- -- Active (high-speed) -- mode VCC = 5.0 V, fOSC = 10 MHz Active (mediumspeed) mode VCC = 5.0 V, fOSC = 10 MHz, OSC/128 VCC = 5.0 V, fOSC = 10 MHz --
-- -- -- -- -- -- 7.0
30.0 80.0 15.0 50.0 15.0 15.0 10.0 mA *3 *4 *2 *1 *2 *1
SER
2.2
3.0
mA
*3 *4
--
3.8
5.0
mA
*3 *4
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (5) VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Values Item Symbol Applicable Pins VCC Test Condition VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /2) VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /8) Subsleep ISUBSP mode current consumption IWATCH Watch mode current consumption VCC VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /2) VCC = 2.7 V, LCD not used, 32-kHz crystal resonator used Min -- Typ 15.0 Max 30.0 Unit A Notes *3 *4
Subactive ISUB mode current consumption
--
8.0
--
*3 *4 Reference value
--
7.5
16.0
A
*3 *4
VCC
--
3.8
6.0
A
*2 *3 *4
2.8
*1 *3 *4
ISTBY Standby mode current consumption RAM data VRAM retaining voltage
VCC
32-kHz crystal resonator not used
--
1.0
5.0
A
*3 *4
VCC
1.5
--
--
V
Rev. 6.00 Mar 15, 2005 page 385 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (6) VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Applicable Pins Test Condition Values Min Typ -- Max 2.0 Unit mA Notes
Item Allowable output low current (per pin)
Symbol IOL
Output pins VCC = 4.0 V to -- except ports 3 5.5 V and 9 Port 3 Output pins except port 9 P90 to P92 VCC = 4.0 V to -- 5.5 V -- VCC = 2.2 V to -- 5.5 V -- -- P93 to P95 --
-- -- -- -- -- -- --
10.0 0.5 25.0 15.0 10.0 10.0 40.0 mA *5
Allowable output high -IOH current (per pin)
Notes: 1. Applies to the mask-ROM version. 2. Applies to the HD6473802. 3. Pin states when current consumption is measured
Rev. 6.00 Mar 15, 2005 page 386 of 502 REJ09B0024-0600
Allowable output high current (total)
Allowable output low current (total)
IOL
Output pins VCC = 4.0 V to -- except ports 3 5.5 V and 9 Port 3 Output pins except port 9 Port 9 VCC = 4.0 V to -- 5.5 V -- --
-- -- -- -- -- -- --
80.0 20.0 80.0 2.0 0.2 15.0 10.0 mA mA
All output pins VCC = 4.0 V to -- 5.5 V Other than above --
-IOH
All output pins VCC = 4.0 V to -- 5.5 V Other than above --
Section 17 Electrical Characteristics
LCD Power Supply Stops
Active (high-speed) mode (IOPE1) Active (mediumspeed) mode (IOPE2) Sleep mode Subactive mode Subsleep mode
VCC
Watch mode
Standby mode
Notes: 4. Except current which flows to the pull-up MOS or output buffer 5. When the PIOFF bit in the port mode register 9 is 0 6. When the PIOFF bit in the port mode register 9 is 1
SER
VCC VCC VCC VCC VCC
Mode
Pin
Internal State Only CPU operates
Other Pins VCC
Oscillator Pins System clock: crystal resonator Subclock: Pin X1 = GND
Only timers operate Only CPU operates Only timers operate CPU stops Only clock time base operates CPU stops CPU and timers both stop
VCC VCC VCC
Stops Stops Stops System clock: crystal resonator Subclock: crystal resonator
VCC
Stops
VCC
Stops
System clock: crystal resonator Subclock: Pin X1 = GND
Rev. 6.00 Mar 15, 2005 page 387 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.2.3
AC Characteristics
Table 17.3 lists the control signal timing and table 17.4 lists the serial interface timing. Table 17.3 Control Signal Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Applicable Pins Test Condition OSC1, OSC2 Values Min Typ -- -- -- -- -- Max 16.0 10.0 4.0 500 ns (1000) 500 (1000) Other than above 250 -- 500 (1000) System clock () cycle time Subclock oscillation frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time trc OSC1, OSC2 tcyc 2 -- fW X1, X2 -- -- -- 32.768 or 38.4 30.5 or 26.0 -- -- 20 -- -- -- 128 128 -- tOSC s kHz Figure 17.1*2 Unit MHz Reference Figure
Item System clock oscillation frequency
Symbol fOSC
VCC = 4.5 V to 5.5 V 2.0 VCC = 2.7 V to 5.5 V 2.0 Other than above 2.0
OSC clock (OSC) cycle time
tOSC
OSC1, OSC2
VCC = 4.5 V to 5.5 V 62.5 VCC = 2.7 V to 5.5 V 100
tW tsubcyc
X1, X2
-- 2 2 VCC = 2.2 V to 5.5 V -- in figure 17.7 Other than above --
-- 8 -- 45 50 2.0 10.0
s tW tcyc tsubcyc s ms s
Figure 17.1 *1
Figure 17.7
X1, X2
VCC = 2.7 V to 5.5 V -- VCC = 2.2 V to 5.5 V --
*3
Rev. 6.00 Mar 15, 2005 page 388 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Applicable Pins Test Condition OSC1 Values Min Typ -- -- -- Max -- -- -- s ns Figure 17.1 Unit ns Reference Figure Figure 17.1
Item External clock high width
Symbol tCPH
VCC = 4.5 V to 5.5 V 25 VCC = 2.7 V to 5.5 V 40 Other than above 100 -- VCC = 4.5 V to 5.5 V 25 VCC = 2.7 V to 5.5 V 40 Other than above 100 -- VCC = 4.5 V to 5.5 V -- VCC = 2.7 V to 5.5 V -- Other than above -- -- VCC = 4.5 V to 5.5 V -- VCC = 2.7 V to 5.5 V -- Other than above -- -- 10 2
X1 External clock low width tCPL OSC1
15.26 or -- 13.02 -- -- -- -- -- --
X1 External clock rise time tCPr OSC1
15.26 or -- 13.02 -- -- -- -- -- -- -- -- -- -- 6 10 25 55.0 6 10 25 55.0 -- --
s ns Figure 17.1
X1 External clock fall time tCPf OSC1
ns ns Figure 17.1
X1
ns tcyc tcyc tsubcyc Figure 17.2 Figure 17.3
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. Values in parentheses indicate tOSC max. when the external clock is used. 3. After powering on, hold VCC at 2.2 V to 5.5 V until the oscillation stabilization time has elapsed.
7PKW 0PKW
1QRI 0QRI
Input pin low width
tIL
7PKW 0PKW
1QRI 0QRI
Input pin high width
tIH
SER
, , IRQAEC, to , AEVL, AEVH , , IRQAEC, to , AEVL, AEVH
pin low width
tREL
SER
0.5 2
-- --
-- --
tOSC tcyc tsubcyc Figure 17.3
0.5
--
--
tOSC
Rev. 6.00 Mar 15, 2005 page 389 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.4 Serial Interface (SCI3) Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Values Item Symbol Test Condition Min 4 6 0.4 VCC = 4.0 V to 5.5 V -- Other than above tRXS -- Typ -- -- -- -- -- -- -- -- -- Max -- -- 0.6 1 1 -- -- -- -- ns Figure 17.5 ns Figure 17.5 tscyc Figure 17.4 Unit Reference Figure
Input clock Asynchronous tscyc cycle Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) tSCKW tTXD
tcyc or tsubcyc Figure 17.4
tcyc or tsubcyc Figure 17.5
VCC = 4.0 V to 5.5 V 200.0 Other than above 400.0
tRXH
VCC = 4.0 V to 5.5 V 200.0 Other than above 400.0
Rev. 6.00 Mar 15, 2005 page 390 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.2.4
A/D Converter Characteristics
Table 17.5 shows the A/D converter characteristics. Table 17.5 A/D Converter Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C (product with regular specifications), Ta = -40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product), unless otherwise specified
Applicable Test Pins Condition AVCC AN0 to AN3 AVCC AVCC Values Min 1.8 - 0.3 AVCC = 5.0 V -- -- Typ Max -- -- -- 600 5.5 Unit V Reference Figure *1
Item
Symbol
Analog power supply AVCC voltage Analog input voltage AVIN
AVCC + 0.3 V 1.5 -- mA A *2 Reference value
Analog power supply AIOPE current AISTOP1
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error CAIN RAIN
AVCC AN0 to AN3
-- -- -- -- AVCC = 2.7 V -- to 5.5 V VCC = 2.7 V to 5.5 V AVCC = 2.0 V -- to 5.5 V VCC = 2.0 V to 5.5 V Other than above -- --
-- -- -- -- --
5.0 15.0 10.0 10 2.5
A pF k bit LSB
*3
--
5.5
-- --
7.5 0.5 LSB
*4
Quantization error
Rev. 6.00 Mar 15, 2005 page 391 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Applicable Test Pins Condition Values Min Typ Max -- 3.0 Unit LSB Reference Figure
Item Absolute accuracy
Symbol
AVCC = 2.7 V -- to 5.5 V VCC = 2.7 V to 5.5 V AVCC = 2.0 V -- to 5.5 V VCC = 2.0 V to 5.5 V Other than above --
--
6.0
-- --
8.0 124 s
*4
Conversion time
AVCC = 2.7 V 12.4 to 5.5 V VCC = 2.7 V to 5.5 V Other than above 62
--
124
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. The conversion time is 62 s.
Rev. 6.00 Mar 15, 2005 page 392 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.2.5
LCD Characteristics
Table 17.6 shows the LCD characteristics. Table 17.6 LCD Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified (including subactive mode), Ta = -20C to +75C (product with regular specifications), Ta = - 40C to +85C (product with wide-range temperature specifications), Ta = +75C (bare die product)
Applicable Pins SEG1 to SEG25 COM1 to COM4 Values Test Condition Min Typ -- Max 0.6 Unit V Reference Figure *1
Item Segment driver step-down voltage Common driver step-down voltage LCD power supply split-resistance Liquid crystal display voltage
Symbol VDS
ID = 2 A -- V1 = 2.7 V to 5.5 V ID = 2 A -- V1 = 2.7 V to 5.5 V Between V1 and VSS 0.5 2.2
VDC
--
0.3
V
*1
RLCD VLCD V1
3.0 --
9.0 5.5
M V *2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: VCC V1 V2 V3 VSS.
Rev. 6.00 Mar 15, 2005 page 393 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.3
Absolute Maximum Ratings of H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version)
Table 17.7 lists the absolute maximum ratings. Table 17.7 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Port 9 pin voltage Operating temperature Symbol VCC AVCC Vin AVin VP9 Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to VCC +0.3 Regular specifications: 2 -20 to +75* Wide-range temperature specifications: -40 to +85*3 Bare die product: +75*4 Storage temperature Tstg -55 to +125 C Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. When the operating voltage is VCC = 2.7 to 3.6 V during flash memory reading, the operating temperature ranges from -20C to +75C when programming or erasing the flash memory. When the operating voltage is VCC = 2.2 to 3.6 V during flash memory reading, the operating temperature ranges from -20C to +50C when programming or erasing the flash memory. 3. The operating temperature ranges from -20C to +75C when programming or erasing the flash memory. 4. The current-carrying temperature ranges from -20C to +75C. Unit V V V V V C Note *1
Rev. 6.00 Mar 15, 2005 page 394 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.4
Electrical Characteristics of H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version)
Power Supply Voltage and Operating Ranges
17.4.1
Power Supply Voltage and Oscillation Frequency Range (F-ZTAT Version)
10.0
38.4
fosc(MHz)
fw(kHz)
4.0 2.0 2.2 2.7 3.6 Vcc (V)
32.768
2.2
2.7
3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
4 MHz specification 10 MHz specification
* All operating modes
Power Supply Voltage and Oscillation Frequency Range (Mask ROM Version)
10.0
fosc(MHz) fw(kHz)
38.4 32.768
4.0 2.0 1.8 2.7 3.6 Vcc (V) 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* All operating modes * When a resonator is used, hold Vcc at 2.2 V to 3.6 V from power-on until the oscillation stabilization time has elapsed.
Rev. 6.00 Mar 15, 2005 page 395 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (F-ZTAT Version)
5.0
19.2
SUB (kHz)
2.0 1.0 2.2 2.7 3.6 Vcc (V)
16.384 9.6 8.192 4.8 4.096
(MHz)
2.2
2.7
* Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Subactive mode
3.6 Vcc (V)
* Subsleep mode (except CPU) * Watch mode (except CPU)
625
(kHz)
250 15.625 2.2 2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 396 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (Mask ROM Version)
5.0
19.2
SUB (kHz)
2.0 1.0 1.8 2.7 3.6 Vcc (V)
16.384 9.6 8.192 4.8 4.096
(MHz)
1.8
2.7
* Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Subactive mode
3.6 Vcc (V)
* Subsleep mode (except CPU) * Watch mode (except CPU)
625
(kHz)
250 15.625 1.8 2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 397 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range (F-ZTAT Version)
5.0
(MHz)
(kHz)
625 1.0 2.2 2.7 3.6 AVcc (V) 500 2.7 3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Active (medium-speed) mode * Sleep (medium-speed) mode
Note: When AVcc = 2.2 V to 2.7 V, the operating range is limited to = 1.0 MHz.
Analog Power Supply Voltage and A/D Converter Operating Range (Mask ROM Version)
5.0
(MHz)
(kHz)
625 1.0 1.8 2.7 3.6 AVcc (V) 500 2.7 3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Active (medium-speed) mode * Sleep (medium-speed) mode
Note: When AVcc = 1.8 V to 2.7 V, the operating range is limited to = 1.0 MHz.
Rev. 6.00 Mar 15, 2005 page 398 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.2
DC Characteristics
Table 17.8 lists the DC characteristics. Table 17.8 DC Characteristics One of following conditions is applied unless otherwise specified. Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Values Item Symbol Applicable Pins Test Condition Min VCC x 0.9 Typ -- Max VCC + 0.3 Unit V Notes
,1QRI 0QRI 7PKW 0PKW SER
RXD32 OSC1 X1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 PB0 to PB3 IRQAEC, P95*5
Input high VIH voltage
,
to , , AEVL, AEVH, SCK32 VCC x 0.8 VCC x 0.9 VCC = 1.8 V to 5.5 V VCC x 0.9 VCC x 0.8 -- -- -- --
VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3
V V V V
VCC x 0.8 VCC x 0.9
-- --
AVCC + 0.3 VCC + 0.3
V V
Rev. 6.00 Mar 15, 2005 page 399 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Input low voltage Symbol VIL Applicable Pins Test Condition Min - 0.3 Typ -- Max VCC x 0.1 Unit V Notes
, 5 IRQAEC, P95* , AEVL, AEVH, SCK32 RXD32 OSC1 Input low voltage X1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3, PB0 to PB3 Output high voltage VOH P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3, P31 to P37 P90 to P95 - 0.3 - 0.3 - 0.3 - 0.3 -- -- -- -- VCC x 0.2 VCC x 0.1 VCC x 0.1 VCC x 0.2 V V V V
Output low VOL voltage
Rev. 6.00 Mar 15, 2005 page 400 of 502 REJ09B0024-0600
,1QRI 0QRI 7PKW 0PKW SER
to
,
,
VCC = 2.7 V to 3.6 V VCC - 1.0 -IOH = 1.0 mA -IOH = 0.1 mA VCC - 0.3
--
--
V
--
--
IOL = 0.4 mA
--
--
0.5
V
VCC = 2.2 V to 3.6 V -- IOL = 10.0 mA VCC = 1.8 V to 3.6 V IOL = 8.0 mA
--
0.5
Section 17 Electrical Characteristics
Values Item Input/ output leakage current Symbol | IIL | Applicable Pins , P43, OSC1, X1, P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, IRQAEC, PA0 to PA3, P90 to P95 Test Condition Min Typ -- Max 1.0 Unit A Notes
VIN = 0.5 V to VCC - -- 0.5 V
Pull-up MOS current Input capacitance
-Ip
Cin
Active IOPE1 mode current consumption
SER
VCC
PB0 to PB3 P31 to P37, P50 to P57, P60 to P67 All input pins except power supply pin
VIN = 0.5 V to AVCC - 0.5 V VCC = 3.0 V, VIN = 0.0 V f = 1 MHz, VIN = 0.0 V, Ta = 25C Active (high-speed) mode VCC = 1.8 V, fOSC = 2 MHz Active (high-speed) mode VCC = 3 V, fOSC = 2 MHz
-- 30
-- --
1.0 180 A
--
--
15.0
pF
--
0.4
--
mA
*1 *3 *4 Approx. max. value = 1.1 x Typ.
--
0.6
--
*1 *3 *4 Approx. max. value = 1.1 x Typ.
--
1.0
--
*2 *3 *4 Approx. max. value = 1.1 x Typ.
Active (high-speed) mode VCC = 3 V, fOSC = 4 MHz
--
1.2
--
*1 *3 *4 Approx. max. value = 1.1 x Typ.
--
1.6
2.8
*2 *3 *4 Condition B
Rev. 6.00 Mar 15, 2005 page 401 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Symbol Applicable Pins VCC Test Condition Active (high-speed) mode VCC = 3 V, fOSC = 10 MHz Active (mediumspeed) mode VCC = 1.8 V, fOSC = 2 MHz, OSC/128 Active (mediumspeed) mode VCC = 3 V, fOSC = 2 MHz, OSC/128 Min -- -- Typ 3.1 3.6 Max 6.0 6.0 Unit mA Notes *1 *3 *4 *2 *3 *4 Condition A -- 0.06 -- *1 *3 *4 Approx. max. value = 1.1 x Typ. -- 0.1 -- *1 *3 *4 Approx. max. value = 1.1 x Typ. -- 0.5 -- *2 *3 *4 Approx. max. value = 1.1 x Typ. -- 0.2 -- *1 *3 *4 Approx. max. value = 1.1 x Typ. -- 0.7 1.3 *2 *3 *4 Condition B Active (mediumspeed) mode VCC = 3 V, fOSC = 10 MHz, OSC/128 -- -- 0.6 1.0 1.8 1.8 *1 *3 *4 *2 *3 *4 Condition A
Active IOPE1 mode current consumption IOPE2
VCC
Rev. 6.00 Mar 15, 2005 page 402 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Symbol Applicable Pins VCC Test Condition VCC = 1.8 V, fOSC = 2 MHz Min -- Typ 0.16 Max -- Unit mA Notes *1 *3 *4 Approx. max. value = 1.1 x Typ. -- 0.3 -- *1 *3 *4 Approx. max. value = 1.1 x Typ. *2 *3 *4 Approx. max. value = 1.1 x Typ. VCC = 3 V, fOSC = 4 MHz -- 0.5 -- *1 *3 *4 Approx. max. value = 1.1 x Typ. -- 0.9 2.2 *2 *3 *4 Condition B *1 *3 *4 *2 *3 *4 Condition A Subactive ISUB mode current consumption VCC VCC = 1.8 V, LCD on, 32-kHz crystal resonator used (SUB = W /2) VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /8) -- 6.2 -- A *1 *3 *4
Reference value
Sleep ISLEEP mode current consumption
VCC = 3 V, fOSC = 2 MHz
--
0.6
--
VCC = 3 V, fOSC = 10 MHz
-- --
1.3 1.7
4.8 4.8
--
4.4
--
*1 *3 *4
Reference value
--
8.0
--
*2 *3 *4
Reference value
VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /2)
-- --
10 28
40 50
*1 *3 *4 *2 *3 *4
Rev. 6.00 Mar 15, 2005 page 403 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Symbol Applicable Pins VCC Test Condition VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /2) VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator used, LCD not used VCC = 2.7 V, Ta = 25C, 32-kHz crystal resonator used, LCD not used VCC = 2.7 V, 32-kHz crystal resonator used, LCD not used Standby ISTBY mode current consumption VCC VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator not used VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used RAM data VRAM retaining voltage Allowable IOL output low current (per pin) VCC Min -- Typ 4.6 Max 16 Unit A Notes *3 *4
Subsleep ISUBSP mode current consumption IWATCH Watch mode current consumption
VCC
--
1.2
--
A
*1 *3 *4
Reference value
--
2.0
--
*3 *4
Reference value
--
2.0
6.0
*3 *4
--
0.1
--
A
*1 *3 *4
Reference value
--
0.3
--
*3 *4
Reference value
-- 1.5
1.0 --
5.0 -- V
*3 *4
Output pins except port 9 P90 to P95
-- VCC = 2.2 V to 3.6 V -- Other than above -- -- --
-- -- -- -- --
0.5 10.0 8.0 20.0 60.0
mA
Rev. 6.00 Mar 15, 2005 page 404 of 502 REJ09B0024-0600
Allowable output low current (total)
IOL
Output pins except port 9 Port 9
mA
Section 17 Electrical Characteristics
Values Item Allowable output high current (per pin) Allowable output high current (total) Symbol -IOH Applicable Pins All output pins Test Condition Min Typ -- -- Max 2.0 0.2 Unit mA Notes
VCC = 2.7 V to 3.6 V -- Other than above --
-IOH
All output pins
--
--
10.0
mA
Notes: Connect the TEST pin to VSS. 1. Applies to the mask-ROM version. 2. Applies to the F-ZTAT version. 3. Pin states when current consumption is measured
LCD Power Supply Stops
Active (high-speed) mode (IOPE1) Active (mediumspeed) mode (IOPE2) Sleep mode Subactive mode Subsleep mode
VCC
Watch mode
Standby mode
Notes: 4. Except current which flows to the pull-up MOS or output buffer 5. Used when user mode or boot mode is determined after canceling a reset in the FZTAT version
SER
Mode
Pin
Internal State Only CPU operates
Other Pins VCC
Oscillator Pins System clock: crystal resonator Subclock: Pin X1 = GND
VCC VCC VCC
Only all on-chip timers operate Only CPU operates Only all on-chip timers operate CPU stops
VCC VCC VCC
Stops Stops Stops System clock: crystal resonator Subclock: crystal resonator
VCC
Only clock time base operates CPU stops
VCC
Stops
VCC
CPU and timers both stop
VCC
Stops
System clock: crystal resonator Subclock: Pin X1 = GND
Rev. 6.00 Mar 15, 2005 page 405 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.3
AC Characteristics
Table 17.9 lists the control signal timing and table 17.10 lists the serial interface timing. Table 17.9 Control Signal Timing One of following conditions is applied unless otherwise specified. Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Applicable Pins Values Test Condition Min 2.0 Typ -- Max 10.0 Unit MHz Reference Figure
Item System clock oscillation frequency
Symbol fOSC
OSC1, OSC2 VCC = 2.7 V to 3.6 V in conditions A and C
Other than above in 2.0 condition C and condition B OSC clock (OSC) cycle time tOSC OSC1, OSC2 VCC = 2.7 V to 3.6 V in conditions A and C 100
--
4.0
--
500
ns
Figure 17.1
Other than above in 250 condition C and condition B System clock () cycle time tcyc 2 -- X1, X2 X1, X2 -- -- 2 2
--
500
-- -- 32.768 or 38.4 30.5 or 26.0 -- --
128 64 -- -- 8 --
tOSC s kHz s tW tcyc tsubcyc Figure 17.1 *
Subclock oscillation fW frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time tW tsubcyc
Rev. 6.00 Mar 15, 2005 page 406 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Applicable Pins OSC1, OSC2 Values Test Condition Min Typ 0.8 Max 2.0 Unit ms Reference Figure Figure 17.8
Item Oscillation stabilization time
Symbol trc
VCC = 2.7 V to 3.6 -- V when using crystal resonator in figure 17.8 VCC = 2.2 V to 3.6 -- V when using crystal resonator in figure 17.8 and in conditions B and C Other than above in -- condition C and when using crystal resonator in figure 17.8 VCC = 2.7 V to 3.6 -- V when using ceramic resonator in figure 17.8 and in conditions A and C VCC = 2.2 V to 3.6 -- V when using ceramic resonator (1) in figure 17.8 and in conditions B and C Other than above in -- condition C and when using ceramic resonator (1) in figure 17.8 Other than above -- --
1.2
3.0
4.0
--
20
45
s
20
45
80
--
-- -- --
50 2.0 2.0
ms s
trc
X1, X2
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 3.6 -- V and in conditions B and C Other than above in -- condition C
4.0
--
Rev. 6.00 Mar 15, 2005 page 407 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Applicable Pins OSC1 Values Test Condition VCC = 2.7 V to 3.6 V in conditions A and C Min 40 Typ -- Max -- Unit ns Reference Figure Figure 17.1
Item
Symbol
External clock high tCPH width
Other than above in 100 condition C and condition B X1 External clock low width tCPL OSC1 VCC = 2.7 V to 3.6 V in conditions A and C -- 40
--
--
15.26 or -- 13.02 -- --
s ns Figure 17.1
Other than above in 100 condition C and condition B X1 External clock rise time tCPr OSC1 VCC = 2.7 V to 3.6 V in conditions A and C -- --
--
--
15.26 or -- 13.02 -- 10
s ns Figure 17.1
Other than above in -- condition C and condition B X1 External clock fall time tCPf OSC1 VCC = 2.7 V to 3.6 V in conditions A and C -- --
--
25
-- --
55.0 10
ns ns Figure 17.1
Other than above in -- condition C and condition B X1 -- 10 , 2
--
25
-- -- --
55.0 -- --
ns tcyc Figure 17.2
Rev. 6.00 Mar 15, 2005 page 408 of 502 REJ09B0024-0600
1QRI 0QRI 7PKW 0PKW
Input pin high width
tIH
, IRQAEC, to ,
SER
AEVL, AEVH
pin low width
tREL
SER
Figure 17.3 tcyc tsubcyc
0.5
--
--
tOSC
Section 17 Electrical Characteristics
Applicable Pins Values Test Condition , Min 2 Typ -- Max -- Unit Reference Figure
Item Input pin low width
Symbol tIL
Note:
*
Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
1QRI 0QRI 7PKW 0PKW
, IRQAEC, to ,
Figure 17.3 tcyc tsubcyc
AEVL, AEVH
0.5
--
--
tOSC
Rev. 6.00 Mar 15, 2005 page 409 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.10 Serial Interface (SCI3) Timing One of following conditions is applied unless otherwise specified. Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Test Condition Values Min 4 6 tSCKW tTXD tRXS tRXH 0.4 -- 400.0 400.0 Typ Max Unit -- -- -- -- -- -- -- -- 0.6 1 -- -- tscyc tcyc or tsubcyc ns ns Figure 17.4 Figure 17.5 Figure 17.5 Figure 17.5 tcyc or tsubcyc Reference Figure Figure 17.4
Item Input clock Asynchronous cycle Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
Symbol tscyc
Rev. 6.00 Mar 15, 2005 page 410 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.4
A/D Converter Characteristics
Table 17.11 shows the A/D converter characteristics. Table 17.11 A/D Converter Characteristics One of following conditions is applied unless otherwise specified. Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Applicable Test Pins Condition AVCC Condition A Condition B Condition C Analog input voltage AVIN AN0 to AN3 AVCC AVCC AVCC = 3.0 V Values Min 2.7 2.2 1.8 - 0.3 -- -- Typ -- -- -- -- -- 600 Max 3.6 3.6 3.6 AVCC + 0.3 V 1.0 -- mA A *2 Reference value AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) CAIN RAIN AVCC AN0 to AN3 -- -- -- -- -- -- -- -- 5.0 15.0 10.0 10 A pF k bit *3 Unit V Reference Figure *1
Item
Symbol
Analog power supply AVCC voltage
Analog power supply AIOPE current AISTOP1
Rev. 6.00 Mar 15, 2005 page 411 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Applicable Test Pins Condition AVCC = 2.7 V to 3.6 V AVCC = 2.2 V to 3.6 V in condition B, AVCC = 2.0 V to 3.6 V in condition C Other than above in condition C Quantization error Absolute accuracy AVCC = 2.7 V to 3.6 V AVCC = 2.2 V to 3.6 V in condition B, AVCC = 2.0 V to 3.6 V in condition C Other than above in condition C Conversion time AVCC = 2.7 V to 3.6 V Other than above Values Min -- -- Typ -- -- Max 3.5 5.5 Unit LSB Reference Figure
Item Nonlinearity error
Symbol
--
--
7.5
*4
-- -- --
-- 2.0 2.5
0.5 4.0 6.0
LSB LSB
--
2.5
8.0
*4
12.4 62
-- --
124 124
s
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. The conversion time is 62 s.
Rev. 6.00 Mar 15, 2005 page 412 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.5
LCD Characteristics
Table 17.12 shows the LCD characteristics. Table 17.12 LCD Characteristics One of following conditions is applied unless otherwise specified. Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Applicable Pins SEG1 to SEG25 COM1 to COM4 Values Test Condition Min Typ -- Max 0.6 Unit V Reference Figure *1
Item Segment driver step-down voltage Common driver step-down voltage LCD power supply split-resistance Liquid crystal display voltage
Symbol VDS
-- ID = 2 A V1 = 2.7 V to 3.6 V ID = 2 A -- V1 = 2.7 V to 3.6 V Between V1 and VSS 1.5 2.2
VDC
--
0.3
V
*1
RLCD VLCD V1
3.0 --
7.0 3.6
M V *2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: VCC V1 V2 V3 VSS.
Rev. 6.00 Mar 15, 2005 page 413 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.6
Flash Memory Characteristics
Table 17.13 Flash Memory Characteristics Condition A: AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (range of operating voltage when reading), VCC = 3.0 V to 3.6 V (range of operating voltage when programming/erasing), Ta = -20C to +75C (range of operating temperature when programming/erasing: product with regular specifications, product with wide-range temperature specifications, bare die product) AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.2 V to 3.6 V (range of operating voltage when reading), VCC = 3.0 V to 3.6 V (range of operating voltage when programming/erasing), Ta = -20C to +50C (range of operating temperature when programming/erasing: product with regular specifications)
Test Conditions Values Min -- -- Typ 7 100 Max 200 Unit ms/ 128 bytes
Condition B:
Item Programming time*1*2*4 Erase time*1*3*5 Reprogramming count Data retain period Programming Wait time after SWE-bit setting*1 Wait time after PSU-bit setting*1 Wait time after P-bit setting*1*4
Symbol tP tE NWEC tDRP x y z1 z2 z3 Wait time after P-bit clear*1 Wait time after 1 PSU-bit clear* Wait time after PV-bit setting*1 Wait time after dummy write*1 Wait time after 1 PV-bit clear*
1200 ms/ block times year s s s s s s s s s s
1000*8 10000*9 -- 10*10 -- -- 1 50 1n6 7 n 1000 28 198 -- -- 30 200 10 -- -- -- -- -- -- -- 32 202 12 -- -- -- -- --
8 Additional programming 5 5 4 2 2
Rev. 6.00 Mar 15, 2005 page 414 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Item Programming Wait time after SWE-bit clear*1 Maximum programming 145 count* * * Erase Wait time after 1 SWE-bit setting* Wait time after ESU-bit setting*1 Wait time after E-bit setting*1*6 Wait time after 1 E-bit clear* Wait time after ESU-bit clear*1 Wait time after EV-bit setting*1 Wait time after dummy write*1 Wait time after EV-bit clear*1 Wait time after SWE-bit clear*1 Maximum erase 167 count* * *
Notes:
Symbol N
Test Conditions
Values Min 100 -- Typ -- -- Max -- Unit s
1000 times
x y z N
1 100 10 10 10 20 2 4 100 --
-- -- -- -- -- -- -- -- -- --
-- -- 100 -- -- -- -- -- -- 120
s s ms s s s s s s times
1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = Wait time after P-bit setting (z) * maximum number of writes (N) 5. The maximum number of writes (N) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) * maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)).
Rev. 6.00 Mar 15, 2005 page 415 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. Reference value when the temperature is 25C (normally reprogramming will be performed by this count). 10. This is a data retain characteristic when reprogramming is performed within the specification range including this minimum value.
17.5
Absolute Maximum Ratings of H8/38104 Group (F-ZTAT Version, Mask ROM Version)
Table 17.14 lists the absolute maximum ratings. Table 17.14 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Port 9 pin voltage Operating temperature Other than port B Port B Symbol VCC CVCC AVCC Vin AVin VP9 Topr Value -0.3 to +7.0 -0.3 to +4.3 -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to VCC +0.3 Regular specifications: 2 -20 to +75* Wide-range temperature specifications: -40 to +85*2 Storage temperature Tstg -55 to +125 C Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. The operating temperature ranges from -20C to +75C when programming or erasing the flash memory. Unit V V V V V V C Note *1
Rev. 6.00 Mar 15, 2005 page 416 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6
Electrical Characteristics of H8/38104 Group (F-ZTAT Version, Mask ROM Version)
Power Supply Voltage and Operating Ranges
17.6.1
Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected)
20.0
fosc (MHz)
fW (kHz)
2.0 2.7 5.5 VCC (V)
32.768
2.7 * All operating modes
5.5 VCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Power Supply Voltage and Oscillation Frequency Range (On-Chip Oscillator Selected)
fosc (MHz)
fW (kHz)
2.0 0.7 2.7 5.5 VCC (V)
32.768
2.7 * All operating modes
5.5 VCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Rev. 6.00 Mar 15, 2005 page 417 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected)
10.0
(MHz)
16.384
1.0
SUB (kHz)
2.7
5.5 VCC (V)
8.192
* Active (high-speed) mode * Sleep (high-speed) mode (except CPU)
4.096
2.7 * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU)
5.5 VCC (V)
1250
(kHz)
15.625 2.7 5.5 VCC (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 418 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected)
16.384 (MHz)
SUB (kHz) 2.7 5.5 VCC (V)
8.192
1.0 0.35
4.096
2.7
* Active (high-speed) mode * Sleep (high-speed) mode (except CPU)
5.5 VCC (V)
* Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU)
(kHz)
125 6.25 2.7 5.5 VCC (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 419 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected)
10.0
(MHz)
(kHz)
1.0 2.7 5.5 AVCC (V)
1000 500 2.7 5.5 AVCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Active (medium-speed) mode * Sleep (medium-speed) mode
Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator Selected)
1.0
(MHz)
(kHz)
0.35 2.7 5.5 AVCC (V)
125 6.25 2.7 5.5 AVCC (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Active (medium-speed) mode * Sleep (medium-speed) mode
Rev. 6.00 Mar 15, 2005 page 420 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.2
DC Characteristics
Table 17.15 lists the DC characteristics. Table 17.15 DC Characteristics (1) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values Item Symbol Applicable Pins Test Condition Min Typ -- Max VCC + 0.3 Unit V Notes
Note: Connect the TEST pin to VSS.
,1QRI 0QRI 7PKW 0PKW SER
RXD32 OSC1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 PB0 to PB3 IRQAEC, P95*5
Input high VIH voltage
,
VCC = 4.0 V to 5.5 V VCC * 0.8
to , , AEVL, AEVH, SCK32
Other than above
VCC * 0.9
-- -- -- -- -- --
VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V
VCC = 4.0 V to 5.5 V VCC * 0.7 Other than above VCC * 0.8
VCC = 4.0 V to 5.5 V VCC * 0.8 Other than above VCC * 0.9
VCC = 4.0 V to 5.5 V VCC * 0.7
Other than above
VCC * 0.8
--
VCC + 0.3
VCC = 4.0 V to 5.5 V VCC * 0.7 Other than above VCC * 0.8
-- -- -- --
AVCC + 0.3 AVCC + 0.3 VCC + 0.3 VCC + 0.3
V
VCC = 4.0 V to 5.5 V VCC * 0.8 Other than above VCC * 0.9
V
Rev. 6.00 Mar 15, 2005 page 421 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (2) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values Item Input low voltage Symbol VIL Applicable Pins Test Condition Min Typ -- Max VCC * 0.2 Unit V Notes
Output high voltage
VOH
Rev. 6.00 Mar 15, 2005 page 422 of 502 REJ09B0024-0600
,1QRI 0QRI 7PKW 0PKW SER
to RXD32 OSC1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3, PB0 to PB3 P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3
,
VCC = 4.0 V to 5.5 V - 0.3
,
, 5 IRQAEC, P95* , AEVL, AEVH, SCK32
Other than above
- 0.3
-- -- -- -- -- --
VCC * 0.1 VCC * 0.3 VCC * 0.2 VCC * 0.2 VCC * 0.1 VCC * 0.3 V V V
VCC = 4.0 V to 5.5 V - 0.3 Other than above - 0.3
VCC = 4.0 V to 5.5 V - 0.3 Other than above - 0.3
VCC = 4.0 V to 5.5 V - 0.3
Other than above
- 0.3
--
VCC * 0.2
VCC = 4.0 V to 5.5 V VCC - 1.0 -- -IOH = 1.0 mA VCC = 4.0 V to 5.5 V VCC - 0.5 -- -IOH = 0.5 mA -IOH = 0.1 mA VCC - 0.3 --
--
V
--
--
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (3) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values Item Symbol Applicable Pins P40 to P42 P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 P31 to P37 Test Condition Min Typ -- -- Max 0.6 0.5 Unit V Notes
Output low VOL voltage
VCC = 4.0 V to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA --
VCC = 4.0 V to 5.5 V -- IOL = 10 mA VCC = 4.0 V to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA --
-- -- -- -- -- -- -- -- -- --
1.0 0.6 0.5 1.5 1.0 0.8 1.0 0.6 0.5 1.0 A
P90 to P93, P95
VCC = 4.0 V to 5.5 V -- IOL = 15 mA VCC = 4.0 V to 5.5 V -- IOL = 10 mA VCC = 4.0 V to 5.5 V -- IOL = 8 mA IOL = 5 mA IOL = 1.6 mA IOL = 0.4 mA -- -- --
OSC1, X1, P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, IRQAEC, PA0 to PA3, P90 to P93, P95 PB0 to PB3
Pull-up MOS current
-Ip
SER
Input/ output leakage current
| IIL |
, P43
VIN = 0.5 V to VCC - -- 0.5 V
VIN = 0.5 V to AVCC -- - 0.5 V VCC = 5.0 V, VIN = 0.0 V VCC = 2.7 V, VIN = 0.0 V 20 --
-- -- 40
1.0 200 -- A Reference value
P31 to P37, P50 to P57, P60 to P67
Rev. 6.00 Mar 15, 2005 page 423 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (4) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values Item Input capacitance Symbol Cin Applicable Pins All input pins except power supply pin VCC Test Condition f = 1 MHz, VIN = 0.0 V, Ta = 25C Active (high-speed) mode VCC = 2.7 V, fOSC = 2 MHz Min -- Typ -- Max 15.0 Unit A Notes
Active IOPE1 mode current consumption
--
0.6
--
mA
*1 *3 *4 Approx. max. value = 1.1 * Typ. *2 *3 *4 Approx. max. value = 1.1 * Typ.
--
1.0
--
Active (high-speed) mode VCC = 5 V, fOSC = 2 MHz
--
0.8
--
*1 *3 *4 Approx. max. value = 1.1 * Typ. *2 *3 *4 Approx. max. value = 1.1 * Typ.
--
1.5
--
Active (high-speed) mode VCC = 5 V, fOSC = 4 MHz
--
1.6
--
*1 *3 *4 Approx. max. value = 1.1 * Typ.
--
2.0
--
*2 *3 *4 Approx. max. value = 1.1 * Typ.
Active (high-speed) mode VCC = 5 V, fOSC = 10 MHz
-- --
3.3 4.0
7.0 7.0
*1 *3 *4 *2 *3 *4
Rev. 6.00 Mar 15, 2005 page 424 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (5) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values Item Symbol Applicable Pins VCC Test Condition Active (mediumspeed) mode VCC = 2.7 V, fOSC = 2 MHz, OSC/128 Min -- Typ 0.2 Max -- Unit mA Notes *1 *3 *4 Approx. max. value = 1.1 * Typ. -- 0.5 -- *2 *3 *4 Approx. max. value = 1.1 * Typ. Active (mediumspeed) mode VCC = 5 V, fOSC = 2 MHz, OSC/128 -- 0.4 -- *1 *3 *4 Approx. max. value = 1.1 * Typ. -- 0.8 -- *2 *3 *4 Approx. max. value = 1.1 * Typ. Active (mediumspeed) mode VCC = 5 V, fOSC = 4 MHz, OSC/128 -- 0.6 -- *1 *3 *4 Approx. max. value = 1.1 * Typ. -- 0.9 -- *2 *3 *4 Approx. max. value = 1.1 * Typ. *1 *3 *4 *2 *3 *4
IOPE2 Active mode current consumption
Active (mediumspeed) mode VCC = 5 V, fOSC = 10 MHz, OSC/128
-- --
0.9 1.2
3.0 3.0
Rev. 6.00 Mar 15, 2005 page 425 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Symbol Applicable Pins VCC Test Condition VCC = 2.7 V, fOSC = 2 MHz Min -- Typ 0.3 Max -- Unit mA Notes *1 *3 *4 Approx. max. value = 1.1 * Typ. -- 0.8 -- *2 *3 *4 Approx. max. value = 1.1 * Typ. VCC = 5 V, fOSC = 2 MHz -- 0.5 -- *1 *3 *4 Approx. max. value = 1.1 * Typ. *2 *3 *4 Approx. max. value = 1.1 * Typ. VCC = 5 V, fOSC = 4 MHz -- 0.9 -- *1 *3 *4 Approx. max. value = 1.1 * Typ. -- 1.3 -- *2 *3 *4 Approx. max. value = 1.1 * Typ. *1 *3 *4 *2 *3 *4
Sleep ISLEEP mode current consumption
--
0.9
--
VCC = 5 V, fOSC = 10 MHz
-- --
1.5 2.2
5.0 5.0
Rev. 6.00 Mar 15, 2005 page 426 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Symbol Applicable Pins VCC Test Condition VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /8) Min -- Typ 11.3 Max -- Unit A Notes *1 *3 *4
Reference value
Subactive ISUB mode current consumption
--
12.7
--
*2 *3 *4
Reference value
VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /2) Subsleep ISUBSP mode current consumption IWATCH Watch mode current consumption VCC VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (SUB = W /2) VCC = 2.7 V, Ta = 25C, 32-kHz crystal resonator used, LCD not used
-- --
16.3 30
50 50
*1 *3 *4 *2 *3 *4
--
4.0
16
A
*3 *4
VCC
--
1.4
--
*1 *3 *4
Reference value
--
1.8
--
*2 *3 *4
Reference value
VCC = 2.7 V, 32-kHz crystal resonator used, LCD not used Standby ISTBY mode current consumption VCC VCC = 2.7 V, Ta = 25C, 32-kHz crystal resonator not used
--
1.8
6.0
*3 *4
--
0.3
--
A
*1 *3 *4
Reference value
--
0.5
--
*2 *3 *4
Reference value
VCC = 2.7 V, Ta = 25C, SUBSTP (subclock oscillator control register) setting = 1 VCC = 5.0 V, Ta = 25C, 32-kHz crystal resonator not used
--
0.05
--
*4
Reference value
--
0.4
--
*1 *3 *4
Reference value
--
0.6
--
*2 *3 *4
Reference value
Rev. 6.00 Mar 15, 2005 page 427 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Values Item Symbol Applicable Pins VCC Test Condition VCC = 5.0 V, Ta = 25C, SUBSTP (subclock oscillator control register) setting = 1 32-kHz crystal resonator not used RAM data VRAM retaining voltage Allowable IOL output low current (per pin) VCC Min -- Typ 0.16 Max -- Unit Notes *4
Reference value
Standby ISTBY mode current consumption
-- 2.0
1.0 --
5.0 -- V
*3 *4 *6
Output pins except ports 3 and 9 Port 3 Output pins except port 9 Port 9
VCC = 4.0 V to 5.5 V --
--
2.0
mA
VCC = 4.0 V to 5.5 V -- -- VCC = 4.0 V to 5.5 V -- Other than above --
-- -- -- -- --
10.0 0.5 15.0 5.0 40.0 mA
Allowable output high current (per pin) Allowable output high current (total)
Notes: Connect the TEST pin to VSS. 1. Applies to the mask-ROM version. 2. Applies to the F-ZTAT version.
Rev. 6.00 Mar 15, 2005 page 428 of 502 REJ09B0024-0600

Allowable output low current (total)
IOL
Output pins except ports 3 and 9 Port 3 Output pins except port 9 Port 9
VCC = 4.0 V to 5.5 V --
VCC = 4.0 V to 5.5 V -- -- -- VCC = 4.0 V to 5.5 V -- Other than above --
-- -- -- -- --
80.0 20.0 80.0 2.0 0.2 mA
-IOH
All output pins
-IOH
All output pins
VCC = 4.0 V to 5.5 V -- Other than above --
-- --
15.0 10.0
mA
Section 17 Electrical Characteristics 3. Pin states when current consumption is measured.
Active (high-speed) mode (IOPE1) Active (mediumspeed) mode (IOPE2) Sleep mode Subactive mode Subsleep mode
VCC
Watch mode
Standby mode
4. Except current which flows to the pull-up MOS or output buffer 5. Used when user mode or boot mode is determined after canceling a reset in the FZTAT version 6. Voltage maintained in standby mode
SER
VCC VCC VCC VCC VCC
Mode
Pin
Internal State Only CPU operates
Other Pins VCC
LCD Power Supply Stops
Oscillator Pins System clock: crystal resonator Subclock: Pin X1 = GND
Only all on-chip timers operate Only CPU operates Only all on-chip timers operate CPU stops Only clock time base operates CPU stops CPU and timers both stop
VCC VCC VCC
Stops Stops Stops System clock: crystal resonator Subclock: crystal resonator
VCC
Stops
VCC
Stops
System clock: crystal resonator Subclock: Pin X1 = GND
Rev. 6.00 Mar 15, 2005 page 429 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.3
AC Characteristics
Table 17.16 lists the control signal timing and table 17.17 lists the serial interface timing. Table 17.16 Control Signal Timing VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Applicable Pins OSC1, OSC2 On-chip oscillator selected tOSC OSC1, OSC2 On-chip oscillator selected tcyc Values Test Condition Min 2.0 0.7 50.0 500 2 -- X1, X2 X1, X2 -- -- 2 2 trc OSC1, OSC2 X1, X2 External clock high tCPH width External clock low width External clock rise time External clock fall time pin low width tCPL tCPr tCPf tREL OSC1 OSC1 OSC1 OSC1 -- -- 20 20 -- -- 10 Typ -- -- -- -- -- -- 32.768 30.5 -- -- -- -- -- -- -- -- -- Max 20.0 2.0 500 1429 128 182 -- -- 8 -- 20 2.0 -- -- 5 5 -- tOSC s kHz s tW tcyc tsubcyc ms s ns ns ns ns tcyc Figure 17.1 Figure 17.1 Figure 17.1 Figure 17.1 Figure 17.2 Figure 17.1 *1 ns Unit MHz *2 Figure 17.1 Reference Figure
Item System clock oscillation frequency OSC clock (OSC) cycle time
Symbol fOSC
System clock () cycle time
Subclock oscillation fW frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time tW tsubcyc
Rev. 6.00 Mar 15, 2005 page 430 of 502 REJ09B0024-0600
SER
SER
Section 17 Electrical Characteristics
Applicable Pins Values Test Condition , Min 2 Typ -- Max -- Unit Reference Figure
Item Input pin high width
Symbol tIH
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. These characteristics are given as ranges between minimum and maximum values in order to account for factors such as temperature, power supply voltage, and variation among production lots. When designing systems, make sure to give due consideration to the SPEC range. Please see the Web site for this product for actual performance data.
Table 17.17
Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Test Condition Values Min 4 6 tSCKW tTXD tRXS tRXH 0.4 -- 150.0 150.0 Typ Max Unit -- -- -- -- -- -- -- -- 0.6 1 -- -- tcyc or tsubcyc tscyc tcyc or tsubcyc ns ns Reference Figure Figure 17.4
Item Input clock Asynchronous cycle Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
1QRI 0QRI
Input pin low width
tIL
, IRQAEC, to ,
1QRI 0QRI 7PKW 0PKW 7PKW 0PKW
tscyc
, IRQAEC, to ,
Figure 17.3 tcyc tsubcyc
AEVL, AEVH ,
0.5 2
-- --
-- --
tOSC tcyc Figure 17.3 tsubcyc
AEVL, AEVH
0.5
--
--
tOSC
Symbol
Figure 17.4 Figure 17.5 Figure 17.5 Figure 17.5
Rev. 6.00 Mar 15, 2005 page 431 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.4
A/D Converter Characteristics
Table 17.18 shows the A/D converter characteristics. Table 17.18 A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Applicable Test Pins Condition AVCC AN0 to AN3 AVCC AVCC Values Min 2.7 - 0.3 AVCC = 5.0 V -- -- Typ -- -- -- 600 Max 5.5 Unit V Reference Figure *1
Item
Symbol
Analog power supply AVCC voltage Analog input voltage AVIN
AVCC + 0.3 V 1.5 -- mA A *2 Reference value
Analog power supply AIOPE current AISTOP1
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error CAIN RAIN
AVCC AN0 to AN3
-- -- -- -- AVCC = 4.0 V -- to 5.5 V AVCC = 2.7 V -- to 5.5 V
-- -- -- -- -- -- -- 2.0 2.0 --
5.0 15.0 10.0 10 3.5 7.5 0.5 4.0 8.0 124
A pF k bit LSB
*3
Quantization error Absolute accuracy
-- AVCC = 4.0 V -- to 5.5 V AVCC = 2.7 V -- to 5.5 V
LSB LSB
Conversion time
6.2
s
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle.
Rev. 6.00 Mar 15, 2005 page 432 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.5
LCD Characteristics
Table 17.19 shows the LCD characteristics. Table 17.19 LCD Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Applicable Pins SEG1 to SEG25 COM1 to COM4 Values Test Condition Min Typ -- Max 0.6 Unit V Reference Figure *1
Item Segment driver step-down voltage Common driver step-down voltage LCD power supply split-resistance Liquid crystal display voltage
Symbol VDS
ID = 2 A -- V1 = 2.7 V to 5.5 V ID = 2 A -- V1 = 2.7 V to 5.5 V Between V1 and VSS 1.5 2.7
VDC
--
0.3
V
*1
RLCD VLCD V1
3.0 --
7.0 5.5
M V *2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: VCC V1 V2 V3 VSS.
Rev. 6.00 Mar 15, 2005 page 433 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.6
Flash Memory Characteristics Flash Memory Characteristics
Table 17.20
Condition A: AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage when programming/erasing), Ta = -20C to +75C (range of operating temperature when programming/erasing: product with regular specifications, product with widerange temperature specifications)
Item Programming time*1 *2 *4
135 Erase time* * *
Symbol tP tE NWEC tDRP x y z1 z2 z3 Wait time after P-bit clear *1 Wait time after PSU-bit clear *1 Wait time after PV-bit setting *1 Wait time after dummy write*1 Wait time after PV-bit clear *1 Wait time after SWE-bit clear*1 Maximum programming count*1 *4*5 N
Test Conditions
Values Min -- -- 1000*8 10*10 1 50 Typ 7 100 Max 200 1200 Unit ms/128 bytes ms/block times year s s s s s s s s s s s times
Reprogramming count Data retain period Programming Wait time after SWE-bit setting*1 Wait time after 1 PSU-bit setting * Wait time after 14 P-bit setting * *
10000*9 -- -- -- -- 30 200 10 -- -- -- -- -- -- -- -- -- -- 32 202 12 -- -- -- -- -- -- 1000
1n6 7 n 1000 Additional programming
28 198 8 5 5 4 2 2 100 --
Rev. 6.00 Mar 15, 2005 page 434 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Test Conditions Values Min 1 100 10 10 10 20 2 4 100 -- Typ -- -- -- -- -- -- -- -- -- -- Max -- -- 100 -- -- -- -- -- -- 120 Unit s s ms s s s s s s times
Item Erase Wait time after 1 SWE-bit setting* Wait time after ESU-bit setting *1 Wait time after E-bit setting *1 *6 Wait time after E-bit clear *1 Wait time after ESU-bit clear *1 Wait time after EV-bit setting *1 Wait time after dummy write*1 Wait time after EV-bit clear *1 Wait time after SWE-bit clear*1 Maximum erase count*1 *6*7
Symbol x y z N
Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = Wait time after P-bit setting (z) * maximum number of writes (N) 5. The maximum number of writes (N) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) * maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). 8. This minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. Reference value when the temperature is 25C (normally reprogramming will be performed by this count). Rev. 6.00 Mar 15, 2005 page 435 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics 10. This is a data retain characteristic when reprogramming is performed within the specification range including this minimum value.
17.6.7
Power Supply Voltage Detection Circuit Characteristics Power Supply Voltage Detection Circuit Characteristics (1)
Table 17.21
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values Item LVDR operation drop voltage* LVD stabilization time Standby mode current consumption Symbol VLVDRmin VLVDON ISTBY LVDE = 1 VCC = 5.0 V 32 resonator not used Note: * In some cases no reset may occur if the power supply voltage, VCC, drops below VLVDRmin = 1.0 V and then rises, so thorough evaluation is called for. Test Conditions Min 1.0 150 -- Typ -- -- -- Max -- -- 100 Unit V s A
Rev. 6.00 Mar 15, 2005 page 436 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.22
Power Supply Voltage Detection Circuit Characteristics (2)
Using on-chip reference voltage and ladder resistor (VREFSEL = VINTDSEL = VINTUSEL = 0)
Rated Values Item Power supply drop detection voltage Power supply rise detection voltage Reset detection voltage 1*1 Reset detection voltage 2 2* Symbol Test Conditions Min 3.3 3.6 2.0 2.7 Typ 3.7 4.0 2.3 3.3 Max 4.2 4.5 2.7 3.9 Unit V V V V Vint(D)*3 LVDSEL = 0 Vint(U)*3 LVDSEL = 0 Vreset1*3 LVDSEL = 0 Vreset2*3 LVDSEL = 1
Notes: 1. The above function should be used in conjunction with the voltage drop/rise detection function. 2. Low-voltage detection reset should be selected for low-voltage detection reset 2 only. 3. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other. Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the minimum values.
Table 17.23
Power Supply Voltage Detection Circuit Characteristics (3)
Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL and VINTUSEL = 1)
Rated Values Item extD/extU interrupt detection level extD/extU pin input voltage*2 Symbol Vexd VextD*1 VextU*1 Test Condition Min 0.80 VCC = 2.7 to 3.3 V -0.3 Typ 1.20 -- Max 1.60 VCC + 0.3 or AVCC + 0.3, whichever is lower 3.6 or AVCC + 0.3, whichever is lower Unit V V
VCC = 3.3 to 5.5 V -0.3
--
V
Notes: 1. The VextD voltage must always be greater than the VextU voltage. 2. The maximum input voltage of the extD and extU pins is 3.6 V.
Rev. 6.00 Mar 15, 2005 page 437 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.24
Power Supply Voltage Detection Circuit Characteristics (4)
Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL = 0)
Test Condition Rated Values Min Typ 3.08 * Vref1 -- 3.33 * Vref2 -- 1.91 * Vref3 -- 2.76 * Vref4 -- Max 3.08 * (Vref1 + 0.1) 1.68 3.33 * (Vref2 + 0.1) 1.55 1.91 * (Vref3 + 0.1) 2.77 2.76 * (Vref4 + 0.1) 1.89 Unit V V V V V V V V
Item Power supply drop detection voltage Vref input voltage (Vint(D)) Power supply rise detection voltage Vref input voltage (Vint(U)) Reset detection voltage 1 Vref input voltage (Vreset1) Reset detection voltage 2 Vref input voltage (Vreset2) Notes:
Symbol Vint(D) Vref1*
2
*1
LVDSEL = 0 3.08 * (Vref1 - 0.1) Vint(D) 0.98
1 Vint(U) * LVDSEL = 0 3.33 * (Vref2 - 0.1) 2
Vref2*
Vint(U)
1
0.91
Vreset1* LVDSEL = 0 1.91 * (Vref3 - 0.1) Vref3*
2
Vreset1
1
0.89
Vreset2* LVDSEL = 1 2.76 * (Vref4 - 0.1) Vref4*
2
Vreset2
1.08
1. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other. Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the minimum values. < Vint(D), Vint(U), Vreset2 < Vreset1 * (Vref1 + * (Vref2 + * (Vref3 + * (Vref4 + 0.1) 0.1) 0.1) 0.1) < 5.5 V (= VCC max) < 5.5 V (= VCC max)
2. The Vref input voltage is calculated using the following formula. 2.7 V (= VCC min) 1.5 V (= RAM retention voltage) Vref1: Vref2: Vref3: Vref4: 2.7 < 2.7 < 1.5 < 2.7 < 3.08 3.33 1.91 2.76
* (Vref1 - 0.1), 3.08 * (Vref2 - 0.1), 3.33 * (Vref3 - 0.1), 1.91 * (Vref4 - 0.1), 2.76
< 5.5 0.98 < Vref1 < 1.68 < 5.5 0.91 < Vref2 < 1.55 < 5.5 0.89 < Vref3 < 2.77 < 5.5 1.08 < Vref4 < 1.89
Rev. 6.00 Mar 15, 2005 page 438 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.25
Power Supply Voltage Detection Circuit Characteristics (5)
Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL = VINTUSEL = 1)
Rated Values Item Comparator detection accuracy extD/extU pin input voltage Symbol Vcdl VextD* VextU* Test Condition | VextU - Vref | | VextD - Vref | VCC = 2.7 to 3.3 V -0.3 -- VCC + 0.3 or AVCC + 0.3, whichever is lower 3.6 or AVCC + 0.3, whichever is lower 2.8 V Min 0.1 Typ -- Max -- Unit V
VCC = 3.3 to 5.5 V -0.3
--
V
Vref pin input voltage
Vref5
VCC = 2.7 to 5.5 V 0.8
--
V
Note: * The VextD voltage must always be greater than the VextU voltage.
17.6.8
Power-On Reset Circuit Characteristics Power-On Reset Circuit Characteristics
Table 17.26
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values Item RES pin pull-up resistance Power-on reset start voltage Symbol Test Condition RRES Vpor Min 65 -- Typ 100 -- Max -- 100 Unit k mV
Note: Make sure to drop the power supply voltage, VCC, to below Vpor = 100 mV and then raise it after the RES pin load had thoroughly dissipated. To drain the load of the RES pin, attaching a diode to the VCC side is recommended. The power-on reset function may not work properly if the power supply voltage, VCC, is raised from a level exceeding 100 mV.
Rev. 6.00 Mar 15, 2005 page 439 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.9
Watchdog Timer Characteristics Watchdog Timer Characteristics
Table 17.27
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Applicable Pins Test Condition VCC = 5 V Rated Values Min 0.2 Typ 0.4 Max -- Unit s Note *
Item On-chip oscillator overflow time
Symbol tOVF
Note: * When the watchdog on-chip oscillator is selected, the timer counts from 0 to 255, indicating the time remaining until an internal reset is generated.
17.7
Operation Timing
Figures 17.1 to 17.5 show the operation timings.
tOSC, tW
OSC1,
X1
VIH VIL
tCPH tcpr
tCPL tCPf
Figure 17.1 Clock Input Timing
VIL
tREL
, to IRQAEC,
, ,
VIH VIL tIL tIH
AEVL, AEVH
Figure 17.3 Input Timing
Rev. 6.00 Mar 15, 2005 page 440 of 502 REJ09B0024-0600
SER
Figure 17.2
Low Width Timing
Section 17 Electrical Characteristics
tSCKW
SCK32
tscyc
Figure 17.4 SCK3 Input Clock Timing
tscyc
SCK32
VIH or VOH* VIL or VOL* tTXD
TXD32 (transmit data)
VOH* VOL* tRXS tRXH
RXD32 (receive data)
Note: * Output timing reference levels Output high Output low VOH = 1/2VCC + 0.2 V VOL = 0.8 V
Load conditions are shown in figure 17.6.
Figure 17.5 SCI3 Input/Output Timing in Clocked Synchronous Mode
Rev. 6.00 Mar 15, 2005 page 441 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.8
Output Load Condition
VCC
2.4 k LSI output pin
30 pF
12 k
Figure 17.6 Output Load Circuit
Rev. 6.00 Mar 15, 2005 page 442 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.9
Resonator Equivalent Circuit
LS CS RS
OSC1 CO
OSC2
Crystal Resonator Parameter Frequency (MHz) RS (max) CO (max) 4 4.193 10
Ceramic Resonator Parameter Frequency (MHz) RS (max) CO (max) 2 18.3 4 6.8 10 4.6
100 100 30 16 pF 16 pF 16 pF
36.94 pF 36.72 pF 32.31 pF
Figure 17.7 Resonator Equivalent Circuit
LS CS RS
OSC1 CO
OSC2
Crystal Resonator Parameter (Nominal Values by Manufacturer) Frequency
Rs (max) Co (max)
Ceramic Resonator Parameter (1) (Nominal Values by Manufacturer) Frequency
Rs (max) Co (max)
4
100 16pF
Manufacturer
NIHON DEMPA KOGYO CO., LTD.
2
Manufacturer
18.3 Murata Manufacturing 36.94pF Co., Ltd.
Ceramic Resonator Parameter (2) (Nominal Values by Manufacturer) Frequency
Rs (max) Co (max)
10
4.6
Manufacturer
Murata Manufacturing 32.31pF Co., Ltd.
Figure 17.8 Resonator Equivalent Circuit
Rev. 6.00 Mar 15, 2005 page 443 of 502 REJ09B0024-0600
Section 17 Electrical Characteristics
17.10
Usage Note
The ZTAT, F-ZTAT, and mask ROM versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the ZTAT or F-ZTAT version, the same evaluation testing should also be conducted for the mask ROM version when changing over to that version.
Rev. 6.00 Mar 15, 2005 page 444 of 502 REJ09B0024-0600
Appendix A Instruction Set
Appendix A Instruction Set
A.1 Instruction List
Operation Notation
Symbol Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx:3/8/16 d:8/16 @aa:8/16 + - x / Description General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits ) Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move Logical complement
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Appendix A Instruction Set
Condition Code Notation
Symbol Description Changed according to execution result * 0 -- Undetermined (no guaranteed value) Cleared to 0 Not affected by execution result
Rev. 6.00 Mar 15, 2005 page 446 of 502 REJ09B0024-0600
Table A.1
Operand Size
Mnemonic #xx:8/16 2 2 2 4 2 Rs16+1Rs16 B B B B B 2 4 2 4 @aa:16Rd8 Rs8@Rd16 Rs8@(d:16, Rd16) Rd16-1Rd16 Rs8@Rd16 B B W W W W W 2 4 2 2 4 4 2 Rs8@aa:8 Rs8@aa:16 #xx:16Rd Rs16Rd16 @Rs16Rd16 @(d:16, Rs16)Rd16 @Rs16Rd16 Rs16+2Rs16 W W W 4 2 4 @aa:16Rd16 Rs16@Rd16 Rs16@(d:16, Rd16) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 @aa:8Rd8 -- -- -- -- -- -- -- -- -- -- @Rs16Rd8 @(d:16, Rs16)Rd8 @Rs16Rd8 Rs8Rd8 -- -- -- -- #xx:8Rd8 -- -- -- -- -- -- Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC) @@aa -- I H N
Addressing Modes/Instruction Length (bytes) Operation Z
Condition Code V 0 0 0 0 0 C -- -- -- -- --
MOV B B B B B
MOV.B #xx:8, Rd
Instruction Set
Number of Execution States
2 2 4 6 6 0 0 0 0 0 -- -- -- -- -- 4 6 4 6 6 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 4 6 4 2 4 6 6 0 0 0 -- -- -- 6 4 6
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @-Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 447 of 502 REJ09B0024-0600
MOV.W Rs, @(d:16, Rd)
Operand Size
Mnemonic Operation @@aa -- Rd16-2Rd16 Rs16@Rd16 W W SP+2SP W 2 SP-2SP Rs16@SP B B W B B W W B B B W B B 2 2 2 2 2 2 2 2 2 2 2 2 2 Rd8+#xx:8Rd8 Rd8+Rs8Rd8 Rd16+Rs16Rd16 Rd8+#xx:8+CRd8 Rd8+Rs8+CRd8 Rd16+1Rd16 Rd16+2Rd16 Rd8+1Rd8 Rd8 decimal adjustRd8 Rd8-Rs8Rd8 Rd16-Rs16Rd16 Rd8-#xx:8-CRd8 Rd8-Rs8-CRd8 -- -- -- (1) -- -- -- -- -- -- -- -- (1) -- -- -- -- -- * -- -- 2 @SPRd16 4 Rs16@aa:16 -- -- -- -- I -- H -- #xx:8/16 2 Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes)
Condition Code N Z V 0 C --
Number of Execution States
Appendix A Instruction Set
MOV W
MOV.W Rs, @-Rd
6
MOV.W Rs, @aa:16
0 0
-- --
6 6
Rev. 6.00 Mar 15, 2005 page 448 of 502 REJ09B0024-0600
0 -- 6 2 2 2 (2) (2) -- -- -- -- ---- ---- -- * (3) 2 2 2 2 2 2 2 2 (2) (2) 2 2
POP
POP Rd
PUSH
PUSH Rs
ADD
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDX
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS
ADDS.W #1, Rd
ADDS.W #2, Rd
INC
INC.B Rd
DAA
DAA.B Rd
SUB
SUB.B Rs, Rd
SUB.W Rs, Rd
SUBX
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
Operand Size
Mnemonic Operation @@aa -- Rd16-1Rd16 Rd16-2Rd16 Rd8-1Rd8 Rd8 decimal adjustRd8 0-RdRd Rd8-#xx:8 2 2 2 2 Rd8-Rs8 Rd16-Rs16 Rd8xRs8Rd16 Rd16 / Rs8Rd16 (RdH: remainder, RdL: quotient) B B B B B B B B 2 0 C b7 b0 2 2 2 2 2 2 2 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd8 #xx:8Rd8 Rd8 Rs8Rd8 Rd #xx:8/16 2 2 2 2 2 2 Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes) I
Condition Code H -- -- -- -- -- -- -- -- (1) -- -- -- -- -- -- (5) (6) ---- ---- -- -- -- * * N -- -- Z -- -- V C ---- ---- -- --
SUBS W W B B B B B W B B
SUBS.W #1, Rd
SUBS.W #2, Rd
DEC
DEC.B Rd
DAS
DAS.B Rd
NEG
NEG.B Rd
CMP
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
MULXU
MULXU.B Rs, Rd
DIVXU
DIVXU.B Rs, Rd
AND
AND.B #xx:8, Rd
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
0 0 0 0 0 0 0
-- -- -- -- -- -- --
AND.B Rs, Rd
OR
OR.B #xx:8, Rd
OR.B Rs, Rd
XOR
XOR.B #xx:8, Rd
XOR.B Rs, Rd
NOT
NOT.B Rd
Appendix A Instruction Set
2 2
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SHAL
SHAL.B Rd
Number of Execution States
2 2 2 2 2 2 2 2 14 14 2 2 2 2 2 2
Operand Size
Mnemonic Operation @@aa -- I -- C b7 B 2 C b7 B 2 0 C b7 B 2 b0 -- b0 -- b0 0 -- H #xx:8/16 2 Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes)
Condition Code N -- Z V 0 C
Appendix A Instruction Set
Number of Execution States
2 -- 0 2 -- 0 0 2 -- 0 2 -- -- 0 2 -- -- 0 2 -- C -- 0 2 -- -- -- -- ---- 2 -- -- -- -- ---- 8
SHAR
SHAR.B Rd B
SHLL
SHLL.B Rd
BSET #xx:3, @Rd B 4
(#xx:3 of @Rd16)
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C B 2 b7 b0 b7 B 2 C b7 B 2 b0 b0 C b7 B 2 (#xx:3 of Rd8) 1 1 b0
SHLR
SHLR.B Rd
ROTXL
ROTXL.B Rd
ROTXR ROTXR.B Rd
ROTL
ROTL.B Rd
ROTR
ROTR.B Rd
BSET
BSET #xx:3, Rd
Operand Size
Mnemonic Operation
Addressing Modes/Instruction Length (bytes)
Condition Code
BNOT #xx:3, @Rd
B
4
(#xx:3 of @Rd16) (#xx:3 of @Rd16) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) (Rn8 of @Rd16) 4 (Rn8 of @aa:8)
BNOT #xx:3, @aa:8
B
4
BNOT Rn, Rd B B B B B B 2 4 2 4
B
2
BNOT Rn, @Rd
BTST
BTST #xx:3, Rd
(#xx:3 of Rd8)Z (#xx:3 of @Rd16)Z 4 (#xx:3 of @aa:8)Z (Rn8 of Rd8)Z
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
Appendix A Instruction Set
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BTST Rn, Rd
BNOT Rn, @aa:8
BNOT B 2
BNOT #xx:3, Rd
(#xx:3 of Rd8)
BCLR Rn, @aa:8
B
4
(Rn8 of @aa:8)
(#xx:3 of Rd8)
BCLR Rn, @Rd
B
4
(Rn8 of @Rd16)
BCLR Rn, Rd
B
2
(Rn8 of Rd8)
0 0 0
BCLR #xx:3, @aa:8
B
4
(#xx:3 of @aa:8)
BCLR #xx:3, @Rd
B
4
(#xx:3 of @Rd16)
BCLR B 2
BCLR #xx:3, Rd
(#xx:3 of Rd8)
BSET Rn, @aa:8
B
4 (Rn8 of @aa:8)
BSET Rn, @Rd 1 0
B
4
(Rn8 of @Rd16)
BSET Rn, Rd 1
B
2 (Rn8 of Rd8) 1
1 0 0
BSET B 4 (#xx:3 of @aa:8)
BSET #xx:3, @aa:8
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
--
--
--
--
--
--
-- (Rn8 of @Rd16) -- (Rn8 of @aa:8) -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
Number of Execution States
#xx:8/16
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
@@aa --
I
H
N
Z
V
C
8 2 8 8 2 8 8 2 8 8 2 8
8
2 8 8 2 6 6 2
Operand Size
Mnemonic Operation
Addressing Modes/Instruction Length (bytes)
Condition Code
BTST B B B B B B B B B B B 4 2 4 4 2 4 4 2 4 4 2 4 4 B B B B B B B B B B B B 4 2 4 4 2 4 (#xx:3 of @aa:8)C (#xx:3 of Rd8)C (#xx:3 of @Rd16)C (#xx:3 of @aa:8)C C(#xx:3 of Rd8) C(#xx:3 of @Rd16) C(#xx:3 of @aa:8) (#xx:3 of Rd8) (#xx:3 of @Rd16) (#xx:3 of @aa:8) C(#xx:3 of Rd8)C C(#xx:3 of @Rd16)C C(#xx:3 of @aa:8)C C(#xx:3 of Rd8)C C(#xx:3 of @Rd16)C C(#xx:3 of @aa:8)C C(#xx:3 of Rd8)C C(#xx:3 of @Rd16)C C(#xx:3 of @aa:8)C 4 (#xx:3 of @Rd16)C 2 (#xx:3 of Rd8)C 4 (Rn8 of @aa:8)Z 4 (Rn8 of @Rd16)Z
BTST Rn, @Rd
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- --
Appendix A Instruction Set
BTST Rn, @aa:8
BLD
BLD #xx:3, Rd
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
BILD
BILD #xx:3, Rd
Rev. 6.00 Mar 15, 2005 page 452 of 502 REJ09B0024-0600
-- -- -- -- -- --
Number of Execution States
#xx:8/16
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
@@aa --
I
H
N
Z
V
C
6 6 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6
BILD #xx:3, @Rd
BILD #xx:3, @aa:8
BST
BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
BIST
BIST #xx:3, Rd
BIST #xx:3, @Rd
BIST #xx:3, @aa:8
BAND
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
BIAND
BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8
BOR
BOR #xx:3, Rd
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
Operand Size
Mnemonic Operation @@aa -- C(#xx:3 of Rd8)C 4 4 C(#xx:3 of @aa:8)C C (#xx:3 of Rd8)C 4 4 2 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C (#xx:3 of @Rd16)C C (#xx:3 of @aa:8)C C (#xx:3 of Rd8)C C (#xx:3 of @Rd16)C C (#xx:3 of @aa:8)C 2 C(#xx:3 of @Rd16)C -- -- -- -- -- -- -- -- -- Branching Condition I H -- -- -- -- -- -- -- -- -- #xx:8/16 2 Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes)
Condition Code N -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- V -- -- -- -- -- -- -- -- -- C
BIOR B B B B B B B B B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BIOR #xx:3, Rd
BIOR #xx:3, @Rd
BIOR #xx:3, @aa:8
BXOR
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
BIXOR
BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
BHI d:8
If condition is true then
BLS d:8
BCS d:8 (BLO d:8)
else next;
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 453 of 502 REJ09B0024-0600
BLE d:8
BCC d:8 (BHS d:8)
PC
BRN d:8 (BF d:8)
PC
BCC
BRA d:8 (BT d:8)
PC
PC+d:8 PC+2 CZ=0 CZ=1 PC+d:8 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N V=0 N V=1 Z(N V)=0 Z(N V)=1
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Number of Execution States
2 6 6 2 6 6 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Operand Size
Mnemonic Operation @@aa -- I #xx:8/16 Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes)
Condition Code H -- -- -- -- -- -- -- -- N -- -- -- -- Z -- -- -- -- V -- -- -- -- C -- -- -- --
Appendix A Instruction Set
Number of Execution States
4 6 8 6 -- -- -- -- -- -- 6 -- -- -- -- -- -- 8 -- -- -- -- -- -- 8 -- -- -- -- -- -- 8 10
BSR -- PC@SP 2 SP-2SP
BSR d:8
JSR @aa:16
--
4
SP-2SP PC@SP
JSR @@aa:8
--
2
SP-2SP PC@SP
SP+2SP
SP+2SP
SP+2SP
PC
RTE --
RTE
2
CCR
RTS --
RTS
2
PC
PC
PC
Rev. 6.00 Mar 15, 2005 page 454 of 502 REJ09B0024-0600
-- 2 SP-2SP PC@SP PC Rn16
JSR
JSR @Rn
PC
JMP @@aa:8
--
2 PC @aa:8
aa:16 PC+d:8 aa:16 @aa:8 @SP @SP @SP
JMP @aa:16
--
4 PC
Rn16
JMP -- 2 PC
JMP @Rn
Operand Size
Mnemonic Operation @@aa 2 Transit to power-down mode. #xx:8CCR 2 2 2 2 2 2 4 CCRRd8 CCR#xx:8CCR CCR#xx:8CCR CCR #xx:8CCR Rs8CCR 2 I #xx:8/16 Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes)
Condition Code H N Z V C
SLEEP B B B B B B
SLEEP
LDC
LDC #xx:8, CCR
LDC Rs, CCR
STC
STC CCR, Rd

ANDC
ANDC #xx:8, CCR
ORC
ORC #xx:8, CCR
XORC
XORC #xx:8, CCR
EEPMOV
EEPMOV
if R4L0 Repeat @R5@R6 R5+1R5 R6+1R6 R4L-1R4L Until R4L=0 else next;
Notes: (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Retains its previous value when the result is zero; otherwise cleared to 0.
(3) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(4) The number of states required for execution is 4n + 9 (n = value of R4L). In the
H8/38004 Group, H8/38002S Group and H8/38104 Group, the number of states required for execution is 4n + 8.
(5) Set to 1 when the divisor is negative; otherwise cleared to 0.
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 455 of 502 REJ09B0024-0600
(6) Set to 1 when the divisor is zero; otherwise cleared to 0.
NOP
NOP
PC
PC+2

Number of Execution States
2 2 2 2 2 2 2 2 (4)
Appendix A Instruction Set
A.2
Operation Code Map
Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
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Table A.2
Low High 2 STC OR NEG MOV BHI RTS BCLR BOR MOV ADD ADDX CMP SUBX OR XOR AND MOV BTST BSR RTE JMP MOV* EEPMOV BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE XOR AND NOT SUB DEC SUBS LDC ORC XORC ANDC LDC ADD INC ADDS MOV CMP 3 4 5 6 7 8 9 A B C
0
1
D
E ADDX SUBX
F DAA DAS
0
NOP
SLEEP
1
SHLL
SHAL
ROTXL ROTXR SHLR ROTL ROTR SHAR
Operation Code Map
2
3 BLT BGT JSR BLE
4
BRA
BRN
5
MULXU
DIVXU
6
BSET
BNOT
7
BST BIST BXOR BAND BLT BIOR BIXOR BIAND BILD
Bit manipulation instructions
8
9
A
B
C
D
E
F
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 457 of 502 REJ09B0024-0600
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
Appendix A Instruction Set
A.3
Number of Execution States
The status of execution for each instruction of the H8/300L CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression:
Execution states = I * SI + J * SJ + K * SK + L * SL + M * SM + N * SN
Examples: When an instruction is fetched from the on-chip ROM, and the on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 * 2 + 2 * 2 = 8 When an instruction is fetched from the on-chip ROM, a branch address is read from the on-chip ROM, and the on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 * 2 + 1 * 2+ 1 * 2 = 8
L=M=N=0
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Appendix A Instruction Set
Table A.3
Number of States Required for Execution
Access Location On-Chip Memory SI SJ SK SL SM SN 1 2 or 3* -- 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip peripheral module is accessed. See section 16.1, Register Addresses (Address Order).
Table A.4
Number of Cycles in Each Instruction
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8
Rev. 6.00 Mar 15, 2005 page 459 of 502 REJ09B0024-0600
Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 2 2 2 2
Instruction Mnemonic Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8
Rev. 6.00 Mar 15, 2005 page 460 of 502 REJ09B0024-0600
Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 2 1 2 2 2 2 1 1 2 2 2 2 1 1 1 1 2 2
Instruction Mnemonic BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BSR BST BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8
Rev. 6.00 Mar 15, 2005 page 461 of 502 REJ09B0024-0600
Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 2 2 2 2n+2* 12 1 1 1 1 1 1 1
Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR
Rev. 6.00 Mar 15, 2005 page 462 of 502 REJ09B0024-0600
Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 2 1 1 2 1 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 12 2 2 1 1 1 1 1 1 1 1 1 1 2 2
Instruction Mnemonic MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd 2 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd 1 2 1
MOV.W Rs, @(d:16, Rd) 2 MOV.W Rs, @-Rd MOV.W Rs, @aa:16 MULXU NEG NOP NOT OR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC ROTL ROTR ROTXL ORC #xx:8, CCR ROTL.B Rd ROTR.B Rd ROTXL.B Rd 1 2 1 1 1 1 1 1 1 1 1 1
Rev. 6.00 Mar 15, 2005 page 463 of 502 REJ09B0024-0600
Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 2
Instruction Mnemonic ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP STC SUB ROTXR.B Rd RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd POP PUSH SUBX POP Rd PUSH Rs SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR
Note: n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively.
Rev. 6.00 Mar 15, 2005 page 464 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
Appendix B I/O Port Block Diagrams
B.1 Port 3 Block Diagrams
5*;
PUCR3 VCC VCC PMR3
P3n
PDR3
VSS
PCR3
Internal data bus
AEC module AEVH(P36) AEVL(P37)
Legend: PDR3: PCR3: PMR3: Port data register 3 Port control register 3 Port mode register 3
PUCR3: Port pull-up control register 3 n = 7 or 6
Figure B.1(a) Port 3 Block Diagram (Pins P37 and P36)
Rev. 6.00 Mar 15, 2005 page 465 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
5*;
PUCR3
VCC VCC
PMR2
P35
PDR3
VSS
PCR3
Legend: PDR3: PCR3: PMR2: Port data register 3 Port control register 3 Port mode register 2
PUCR3: Port pull-up control register 3
Figure B.1(b) Port 3 Block Diagram (Pin P35)
Rev. 6.00 Mar 15, 2005 page 466 of 502 REJ09B0024-0600
Internal data bus
Appendix B I/O Port Block Diagrams
5*;
PUCR3
VCC
VCC
Internal data bus
P3n
PDR3
PCR3 VSS
Legend: PUCR3: Port pull-up control register 3 PDR3: PCR3: Port data register 3 Port control register 3
n = 4 or 3
Figure B.1(c) Port 3 Block Diagram (Pins P34 and P33)
Rev. 6.00 Mar 15, 2005 page 467 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
5*;
TMOFH (P32) TMOFL (P31)
PUCR3 VCC VCC PMR3
Internal data bus
P3n
PDR3
VSS
PCR3
Legend: PDR3: PCR3: PMR3: Port data register 3 Port control register 3 Port mode register 3
PUCR3: Port pull-up control register 3 n = 2 or 1
Figure B.1(d) Port 3 Block Diagram (Pins P32 and P31)
Rev. 6.00 Mar 15, 2005 page 468 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
B.2
Port 4 Block Diagrams
PMR2
P43
Internal data bus
143
Legend: PMR2: Port mode register 2
Figure B.2(a) Port 4 Block Diagram (Pin P43)
Rev. 6.00 Mar 15, 2005 page 469 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
5*;
SCINV3 VCC SPC32
SCI3 module
TXD32
Internal data bus
P42
PDR4
PCR4 VSS
Legend: PDR4: Port data register 4 PCR4: Port control register 4
Figure B.2(b) Port 4 Block Diagram (Pin P42)
Rev. 6.00 Mar 15, 2005 page 470 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
5*;
VCC
SCI3 module
RE32 RXD32 P41 PDR4
VSS
Legend: PDR4: Port data register 4 PCR4: Port control register 4 SCINV2
Figure B.2(c) Port 4 Block Diagram (Pin P41)
Rev. 6.00 Mar 15, 2005 page 471 of 502 REJ09B0024-0600
Internal data bus
PCR4
Appendix B I/O Port Block Diagrams
5*;
SCI3 module
VCC
SCKIE32 SCKOE32 SCKO32 SCKI32
P40
PDR4
Internal data bus
PCR4 VSS
Legend: PDR4: Port data register 4 PCR4: Port control register 4
Figure B.2(d) Port 4 Block Diagram (Pin P40)
Rev. 6.00 Mar 15, 2005 page 472 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
B.3
Port 5 Block Diagram
SBY
PUCR5 VCC VCC PMR5
VSS
PCR5
Internal data bus
P5n
PDR5
WKPn
Legend: PDR5: PCR5: PMR5: Port data register 5 Port control register 5 Port mode register 5
PUCR5: Port pull-up control register 5 n = 7 to 0
Figure B.3 Port 5 Block Diagram
Rev. 6.00 Mar 15, 2005 page 473 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
B.4
Port 6 Block Diagram
5*;
PUCR6 VCC
PCR6 P6n
VSS
Legend: PDR6: PCR6: Port data register 6 Port control register 6
PUCR6: Port pull-up control register 6 n = 7 to 0
Figure B.4 Port 6 Block Diagram
Rev. 6.00 Mar 15, 2005 page 474 of 502 REJ09B0024-0600
Internal data bus
VCC
PDR6
Appendix B I/O Port Block Diagrams
B.5
Port 7 Block Diagram
5*;
VCC PDR7
PCR7 P7n
VSS
Legend: PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0
Figure B.5 Port 7 Block Diagram
Rev. 6.00 Mar 15, 2005 page 475 of 502 REJ09B0024-0600
Internal data bus
Appendix B I/O Port Block Diagrams
B.6
Port 8 Block Diagram
5*;
VCC
PCR8 P80
VSS
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure B.6 Port 8 Block Diagram (Pin P80)
Rev. 6.00 Mar 15, 2005 page 476 of 502 REJ09B0024-0600
Internal data bus
PDR8
Appendix B I/O Port Block Diagrams
B.7
Port 9 Block Diagrams
PWM module
PWMn + 1
5*;
Internal data bus
PDR9 VSS Legend: PDR9: Port data register 9 n = 5 to 2
PMR9 P9n PDR9 VSS Legend: PMR9: Port mode register 9 PDR9: Port data register 9 n = 1 or 0
Figure B.7(a) Port 9 Block Diagram (Pins P91 and P90)
5*;
Internal data bus
P9n
Figure B.7(b) Port 9 Block Diagram (Pins P95 to P92)
Rev. 6.00 Mar 15, 2005 page 477 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
SBY
P93 PDR93 VSS
LVD module VREFSEL Vref
PDR9: Port data register 9
Figure B.7(c) Port 9 Block Diagram (Pin P93, H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 478 of 502 REJ09B0024-0600
Internal data bus
Appendix B I/O Port Block Diagrams
B.8
Port A Block Diagram
5*;
VCC PDRA
PCRA PAn
VSS
Legend: PDRA: Port data register A PCRA: Port control register A n = 3 to 0
Figure B.8 Port A Block Diagram
Rev. 6.00 Mar 15, 2005 page 479 of 502 REJ09B0024-0600
Internal data bus
Appendix B I/O Port Block Diagrams
B.9
Port B Block Diagrams
PBn
Internal data bus
A/D module DEC AMR3 to AMR0 VIN
n = 3 to 0
Figure B.9(a) Port B Block Diagram
Rev. 6.00 Mar 15, 2005 page 480 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
PB0
Internal data bus
A/D module DEC AMR3 to AMR0
VIN
LVD module VINTDSEL
extD
Figure B.9(b) Port B Block Diagram (Pin PB0, H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 481 of 502 REJ09B0024-0600
Appendix B I/O Port Block Diagrams
PB1
Internal data bus
A/D module DEC AMR3 to AMR0
VIN
LVD module VINTUSEL
extU
Figure B.9(c) Port B Block Diagram (Pin PB1, H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 482 of 502 REJ09B0024-0600
Appendix C Port States in Each Operating State
Appendix C Port States in Each Operating State
Table C.1
Port
Port States
Reset Sleep Subsleep Retained Retained Retained Retained Retained Retained Retained Retained Standby Watch Subactive Active Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
P37 to P31 High Retained impedance P43 to P40 High Retained impedance P57 to P50 High Retained impedance P67 to P60 High Retained impedance P77 to P70 High Retained impedance P80 High Retained impedance
High Retained impedance* High impedance Retained
Retained High impedance* Retained High impedance* High impedance High impedance High impedance High impedance Retained Retained Retained Retained
P95 to P90 High Retained impedance PA3 to PA0 High Retained impedance
PB3 to PB0 High High High High impedance impedance impedance impedance Note: *
High High High impedance impedance impedance
High level output when the pull-up MOS is in on state.
Rev. 6.00 Mar 15, 2005 page 483 of 502 REJ09B0024-0600
Appendix D Product Code Lineup
Appendix D Product Code Lineup
Table D.1
Product Type H8/3802 PROM version Regular product
Product Code Lineup of H8/3802 Group
Product Code HD6473802H HD6473802FP HD6473802P Product with wide-range temperature specifications Mask ROM version Regular product HD6473802D HD6473802FPI HD6473802Q HD6433802H HD6433802FP HD6433802P HCD6433802 Product with wide-range temperature specifications HD6433802D HD6433802FPI HD6433802Q HD6433801H HD6433801FP HD6433801P HCD6433801 Product with wide-range temperature specifications HD6433801D HD6433801FPI HD6433801Q HD6433800H HD6433800FP HD6433800P HCD6433800 Product with wide-range temperature specifications HD6433800D HD6433800FPI HD6433800Q Model Marking HD6473802H HD6473802FP HD6473802P HD6473802H HD6473802FP HD6473802P HD6433802 (***) H HD6433802 (***) FP HD6433802 (***) P HD6433802 (***) H HD6433802 (***) FP HD6433802 (***) P HD6433801 (***) H HD6433801 (***) FP HD6433801 (***) P HD6433801 (***) H HD6433801 (***) FP HD6433801 (***) P HD6433800 (***) H HD6433800 (***) FP HD6433800 (***) P HD6433800 (***) H HD6433800 (***) FP HD6433800 (***) P Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin DILP (DP-64S)
H8/3801
Mask ROM version
Regular product
H8/3800
Mask ROM version
Regular product
Legend: (***): ROM code Rev. 6.00 Mar 15, 2005 page 484 of 502 REJ09B0024-0600
Appendix D Product Code Lineup
Table D.2
Product Type H8/38004
Product Code Lineup of H8/38004 Group
Product Code Regular product (2.7 V) Regular product (2.2 V) Product with wide-range temperature specifications (2.7 V) Mask ROM version Regular product HD64F38004H10 HD64F38004FP10 HCD64F38004 HD64F38004H4 HD64F38004FP4 HCD64F38004C4 Model Marking 64F38004H10 F38004FP10 64F38004H4 F38004FP4 Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Flash memory version
HD64F38004H10W 64F38004H10 HD64F38004FP10W F38004FP10
HD64338004H HD64338004FP HCD64338004
HD64338004H 38004 (***) FP HD64338004H 38004 (***) FP
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product with wide-range temperature specifications H8/38003 Mask ROM version Regular product
HD64338004HW HD64338004FPW
HD64338003H HD64338003FP HCD64338003
HD64338003H 38003 (***) FP HD64338003H 38003 (***) FP
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product with wide-range temperature specifications
HD64338003HW HD64338003FPW
Rev. 6.00 Mar 15, 2005 page 485 of 502 REJ09B0024-0600
Appendix D Product Code Lineup
Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product Type H8/38002 Flash memory version Regular product (2.7 V) Regular product (2.2 V) Product with wide-range temperature specifications (2.7 V) Mask ROM version Regular product
Product Code HD64F38002H10 HD64F38002FP10 HCD64F38002 HD64F38002H4 HD64F38002FP4 HCD64F38002C4
Model Marking 64F38002H10 F38002FP10 64F38002H4 F38002FP4
HD64F38002H10W 64F38002H10 HD64F38002FP10W F38002FP10
HD64338002H HD64338002FP HCD64338002
HD64338002H 38002 (***) FP HD64338002H 38002 (***) FP
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product with wide-range temperature specifications H8/38001 Mask ROM version Regular product
HD64338002HW HD64338002FPW
HD64338001H HD64338001FP HCD64338001
HD64338001H 38001 (***) FP HD64338001H 38001 (***) FP
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product with wide-range temperature specifications H8/38000 Mask ROM version Regular product
HD64338001HW HD64338001FPW
HD64338000H HD64338000FP HCD64338000
HD64338000H 38000 (***) FP HD64338000H 38000 (***) FP
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Die 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product with wide-range temperature specifications
HD64338000HW HD64338000FPW
Legend: (***): ROM code
Rev. 6.00 Mar 15, 2005 page 486 of 502 REJ09B0024-0600
Appendix D Product Code Lineup
Table D.3
Product Type H8/38002S
Product Code Lineup of H8/38002S Group
Product Code Regular product Product with wide-range temperature specifications HD64338002SH HD64338002SFZ HD64338002SHW Model Marking 38002 (***) H 38002 (***) 38002 (***) H Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K)
Mask ROM version
HD64338002SFZW 38002 (***)
H8/38001S
Mask ROM version
Regular product Product with wide-range temperature specifications
HD64338001SH HD64338001SFZ HD64338001SHW
38001 (***) H 38001 (***) 38001 (***) H
64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K)
HD64338001SFZW 38001 (***)
H8/38000S
Mask ROM version
Regular product Product with wide-range temperature specifications
HD64338000SH HD64338000SFZ HD64338000SHW
38000 (***) H 38000 (***) 38000 (***) H
64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K)
HD64338000SFZW 38000 (***)
Legend: (***): ROM code
Rev. 6.00 Mar 15, 2005 page 487 of 502 REJ09B0024-0600
Appendix D Product Code Lineup
Table D.4
Product Type H8/38104
Product Code Lineup of H8/38104 Group
Product Code Regular product Product with wide-range temperature specifications Mask ROM version Regular product Product with wide-range temperature specifications HD64F38104H HD64F38104FP HD64F38104HW HD64F38104FPW Model Marking F38104H F38104FP F38104H F38104FP Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Flash memory version
HD64338104H HD64338104FP HD64338104HW HD64338104FPW
38104(***)H 38104(***) 38104(***)H 38104(***)
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
H8/38103
Mask ROM version
Regular product Product with wide-range temperature specifications
HD64338103H HD64338103FP HD64338103HW HD64338103FPW
38103(***)H 38103(***) 38103(***)H 38103(***)
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
H8/38102
Flash memory version
Regular product Product with wide-range temperature specifications
HD64F38102H HD64F38102FP HD64F38102HW HD64F38102FPW
F38102H F38102FP F38102H F38102FP
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Mask ROM version
Regular product Product with wide-range temperature specifications
HD64338102H HD64338102FP HD64338102HW HD64338102FPW
38102(***)H 38102(***) 38102(***)H 38102(***)
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
H8/38101
Mask ROM version
Regular product Product with wide-range temperature specifications
HD64338101H HD64338101FP HD64338101HW HD64338101FPW
38101(***)H 38101(***) 38101(***)H 38101(***)
64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Rev. 6.00 Mar 15, 2005 page 488 of 502 REJ09B0024-0600
Appendix D Product Code Lineup
Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E)
Product Type H8/38100 Mask ROM version Regular product Product with wide-range temperature specifications
Product Code HD64338100H HD64338100FP HD64338100HW HD64338100FPW
Model Marking 38100(***)H 38100(***) 38100(***)H 38100(***)
Legend: (***): ROM code
Rev. 6.00 Mar 15, 2005 page 489 of 502 REJ09B0024-0600
Appendix E Package Dimensions
Appendix E Package Dimensions
The package dimensions are shown in figure E.1 (FP-64A), figure E.2 (FP-64E), figure E.3 (FP64K), and figure E.4 (DP-64S).
JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GB-A Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g
HD
*1
D 33
48
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
49
32 bp b1
Reference Symbol
Dimension in Millimeters Min Nom 14 14 2.70 16.9 16.9 17.2 17.2 17.5 17.5 3.05 0.00 0.29 0.10 0.37 0.35 0.12 0.17 0.15 0 0.8 0.15 0.10 1.0 1.0 0.5 0.8 1.6 1.1 8 0.22 0.25 0.45 Max
c1
HE
E
c
D E A2
*2
Terminal cross section
ZE
17 64
HD HE A A1 bp
1 ZD
16
b1 c
A2
F
c1
A
c
A1
L L1
e x y ZD ZE L L1
Detail F
e
*3
y
bp
x
M
Figure E.1 Package Dimensions (FP-64A)
Rev. 6.00 Mar 15, 2005 page 490 of 502 REJ09B0024-0600
Appendix E Package Dimensions
JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KC-A Previous Code FP-64E/FP-64EV MASS[Typ.] 0.4g
HD
*1
D 33
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
48
49
32
bp b1
Reference Symbol
Dimension in Millimeters Min Nom 10 10 1.45 11.8 11.8 12.0 12.0 12.2 12.2 1.70 0.00 0.17 0.10 0.22 0.20 0.12 0.17 0.15 0 0.5 0.08 0.10 1.25 1.25 0.3 0.5 1.0 0.7 8 0.22 0.20 0.27 Max
c1
HE
E
c
D E A2
*2
Terminal cross section
64 17
HD HE A A1
ZE
1 ZD Index mark
16
bp b1 c
A2
A
c
F
c1
A1
L L1
e x y ZD ZE L L1
e
*3
Detail F
bp x M
y
Figure E.2 Package Dimensions (FP-64E)
Rev. 6.00 Mar 15, 2005 page 491 of 502 REJ09B0024-0600
Appendix E Package Dimensions
JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g
HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
49
32
HE
E
Reference Symbol
*2
c1
Dimension in Millimeters Min 9.9 9.9 Nom 10.0 10.0 1.4 11.8 11.8 12.0 12.0 12.2 12.2 1.7 0.05 0.15 0.1 0.20 0.18 0.09 0.145 0.125 0 8 0.5 0.08 0.08 1.25 1.25 0.35 0.5 1.0 0.65 0.20 0.15 0.25 Max 10.1 10.1
c
D 64 E
ZE
17
Terminal cross section
A2 HD
1 Index mark ZD
1
6
HE A A1 F bp b1
A2
A
c c1
A1
y e *3 bp x
c
L L1 Detail F
e x y ZD ZE L L1
Figure E.3 Package Dimensions (FP-64K)
Rev. 6.00 Mar 15, 2005 page 492 of 502 REJ09B0024-0600
Appendix E Package Dimensions
JEITA Package Code P-SDIP64-17x57.6-1.78 RENESAS Code PRDP0064BB-A Previous Code DP-64S/DP-64SV MASS[Typ.] 8.8g
D
64
33
1 b3 Z
32
E
Reference Symbol
Dimension in Millimeters Min Nom 19.05 57.6 17.0 58.5 18.6 5.08 0.51 0.38 0.48 1.0 0.20 0 1.53 1.78 0.25 0.36 15 2.03 1.46 2.54 0.58 Max
A1
e1
A
D E A e bp
L
e1
c
A1 bp b3 c
e Z L
Figure E.4 Package Dimensions (DP-64S)
Rev. 6.00 Mar 15, 2005 page 493 of 502 REJ09B0024-0600
Appendix F Chip Form Specifications
Appendix F Chip Form Specifications
X direction 3.60 0.05 Y direction 3.73 0.05
Maximum dimensions in chip's plane
X direction 3.60 0.25 Y direction 3.73 0.25
Max 0.03
Unit: mm
Figure F.1 Cross-Sectional View of Chip (HCD6433802, HCD6433801, and HCD6433800)
X direction 2.73 0.05 Y direction 3.27 0.05
Maximum dimensions in chip's plane
X direction 2.73 0.25 Y direction 3.27 0.25
Max 0.03
Unit: mm
Figure F.2 Cross-Sectional View of Chip (HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000)
Rev. 6.00 Mar 15, 2005 page 494 of 502 REJ09B0024-0600
0.28 0.02
0.28 0.02
Appendix F Chip Form Specifications
X direction 4.09 0.05 Y direction 3.82 0.05
Maximum dimensions in chip's plane
X direction 4.09 0.25 Y direction 3.82 0.25
Figure F.3 Cross-Sectional View of Chip (HCD64F38004 and HCD64F38002)
Rev. 6.00 Mar 15, 2005 page 495 of 502 REJ09B0024-0600
max 0.03
Unit: mm
0.28 0.02
Appendix A Instruction Set
Appendix G Bonding Pad Form
Bonding area
72m
Metallic film is visible from here
5m
72m
5m
Figure G.1 Bonding Pad Form (HCD6433802, HCD6433801, HCD6433800, HCD64338004, HCD64338003, HCD64338002, HCD64338001, HCD64338000, HCD64F38004, and HCD64F38002)
Rev. 6.00 Mar 15, 2005 page 496 of 502 REJ09B0024-0600
Appendix H Chip Tray Specifications
Appendix H Chip Tray Specifications
51 Chip orientation
3.73 4.0 0.1 5.9 0.1 4.9 0.1
Product name Chip
51
3.60
Chip tray code Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Product code: CT065 Characteristic engraving: TCT4040-060
X
X'
4.0 0.05
0.6 0.1
4.9 0.1
5.9 0.1
1.8 0.1
Cross-sectional view: X to X'
Figure H.1 Chip Tray Specifications (HCD6433802, HCD6433801, and HCD6433800)
Rev. 6.00 Mar 15, 2005 page 497 of 502 REJ09B0024-0600
4.0 0.05
Unit: mm
Appendix H Chip Tray Specifications
51 Chip orientation
3.27 4.0 0.1 5.34 0.1 4.48 0.1
Product name Chip
51
2.73
Chip tray code Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Product code: CT022 Characteristic engraving: TCT036036-060
X
X'
3.6 0.05
0.6 0.1
4.48 0.1
5.34 0.1
1.8 0.1
Cross-sectional view: X to X'
Figure H.2 Chip Tray Specifications (HCD64338004, HCD64338003, HCD64338002, HCD64338001, and HCD64338000)
Rev. 6.00 Mar 15, 2005 page 498 of 502 REJ09B0024-0600
3.6 0.05
Unit: mm
Appendix H Chip Tray Specifications
51 Chip orientation
3.82 4.0 0.1 6.9 0.15 6.2 0.1
Product name Chip
51
4.09
Chip tray code Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Product code: CT015 Characteristic engraving: TCT45-060P
X
X'
4.5 0.05
0.6 0.1
6.2 0.1
6.9 0.1
1.8 0.1
Cross-sectional view: X to X'
Figure H.3 Chip Tray Specifications (HCD64F38004 and HCD64F38002)
Rev. 6.00 Mar 15, 2005 page 499 of 502 REJ09B0024-0600
4.5 0.05
Unit: mm
Appendix H Chip Tray Specifications
Rev. 6.00 Mar 15, 2005 page 500 of 502 REJ09B0024-0600
Index
Index
10-bit PWM ............................................ 309 A/D converter ......................................... 317 Clock pulse generators Prescaler S .......................................... 102 Prescaler W......................................... 102 Subclock generator ............................. 100 System clock generator......................... 96 Exception handling ................................... 73 Reset exception handling...................... 83 Stack status ........................................... 87 Flash memory ......................................... 141 Auto-erase mode................................. 169 Auto-program mode ........................... 167 Boot mode .......................................... 148 Boot program...................................... 148 Erase/erase-verify ............................... 157 Erasing units ....................................... 143 Error protection .................................. 159 Hardware protection ........................... 159 Memory read mode............................. 164 On-board programming modes........... 148 Power-down state ............................... 174 Program/program-verify..................... 153 Programmer mode .............................. 160 Programming units ............................. 143 Socket adapter .................................... 160 Software protection ............................ 159 Status polling ...................................... 172 Status read mode................................. 170 Interrupt Internal interrupts ................................. 85 Interrupt response time ......................... 87 IRQ interrupts....................................... 84 WKP interrupts..................................... 84 Interrupt mask bit (I)................................. 35 LCD controller/driver ............................. 329 LCD display........................................ 339 LCD RAM .......................................... 341 Package ....................................................... 3 Pin arrangement .......................................... 7 Power-down modes................................. 109 Module standby function .................... 128 Sleep mode.......................................... 120 Standby mode ..................................... 121 Subactive mode................................... 122 Subsleep mode .................................... 122 Register ADRR ......................... 319, 367, 371, 374 ADSR.......................... 321, 367, 371, 374 AEGSR ....................... 239, 366, 370, 373 AMR ........................... 320, 367, 371, 374 BRR ............................ 269, 366, 370, 373 CKSTPR1 ................... 114, 368, 372, 375 CKSTPR2 ................... 114, 368, 372, 375 EBR............................. 146, 366, 370, 373 ECCR.......................... 240, 366, 370, 373 ECCSR........................ 241, 366, 370, 373 ECPWCR.................... 237, 366, 370, 373 ECPWDR.................... 238, 366, 370, 373 FENR .......................... 147, 366, 370, 373 FLMCR1..................... 145, 366, 370, 373 FLMCR2..................... 146, 366, 370, 373 FLPWCR .................... 147, 366, 370, 373 IEGR ............................. 77, 368, 372, 375 IENR ............................. 78, 368, 372, 375 IRR................................ 80, 368, 372, 375 IWPR ............................ 82, 368, 372, 375
Rev. 6.00 Mar 15, 2005 page 501 of 502 REJ09B0024-0600
Index
LCR .............................336, 367, 371, 374 LCR2 ...........................338, 367, 371, 374 LPCR ...........................333, 367, 371, 374 OCR.............................222, 367, 371, 374 PCR3 ...........................180, 368, 372, 375 PCR4 ...........................187, 368, 372, 375 PCR5 ...........................191, 368, 372, 375 PCR6 ...........................195, 368, 372, 375 PCR7 ...........................199, 368, 372, 375 PCR8 ...........................201, 368, 372, 375 PCRA...........................206, 368, 372, 375 PDR3 ...........................180, 367, 371, 374 PDR4 ...........................186, 367, 371, 374 PDR5 ...........................191, 368, 371, 374 PDR6 ...........................195, 368, 371, 374 PDR7 ...........................198, 368, 371, 374 PDR8 ...........................201, 368, 371, 374 PDR9 ...........................203, 368, 371, 374 PDRA ..........................206, 368, 371, 374 PDRB ..........................209, 368, 371, 374 PMR2 ..........................183, 367, 371, 374 PMR3 ..........................182, 367, 371, 374 PMR5 ..........................192, 367, 371, 374 PMR9 ..........................204, 368, 372, 375 PMRB..........................209, 368, 372, 375 PUCR3 ........................181, 368, 372, 375 PUCR5 ........................192, 368, 372, 375 PUCR6 ........................196, 368, 372, 375 PWCR..........................312, 367, 371, 374 PWDR .........................314, 367, 371, 374 RDR.............................260, 367, 370, 373 RSR .................................................... 259 SCR3 ...........................264, 366, 370, 373 SMR.............................261, 366, 370, 373 SPCR ...........................187, 366, 370, 373
SSR ............................. 266, 367, 370, 373 SYSCR1...................... 110, 368, 372, 375 SYSCR2...................... 113, 368, 372, 375 TCA ............................ 217, 367, 370, 373 TCR ............................ 223, 367, 371, 374 TCSR .......................... 224, 367, 371, 374 TCSRW....................... 251, 367, 370, 373 TCW ........................... 253, 367, 370, 373 TDR ............................ 260, 367, 370, 373 TMA ........................... 216, 367, 370, 373 TSR..................................................... 260 WEGR........................... 83, 366, 370, 373 Serial communication interface 3 (SCI3) 257 Asynchronous mode ........................... 275 Bit rate ................................................ 269 Break................................................... 303 Clocked synchronous mode ................ 287 Framing error ...................................... 283 Mark state ........................................... 303 Multiprocessor communication function ........................................................ 295 Overrun error ...................................... 283 Parity error .......................................... 283 Timer A................................................... 215 Timer F ................................................... 219 16-bit timer mode ............................... 227 8-bit timer mode ................................. 228 Vector address .......................................... 76 Watchdog timer ...................................... 250
Rev. 6.00 Mar 15, 2005 page 502 of 502 REJ09B0024-0600
Renesas 8-Bit Single-Chip Microcomputer Hardware Manual H8/3802, H8/38004, H8/38002S, H8/38104 Group
Publication Date: 1st Edition, November, 1999 Rev.6.00, March 15, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
Colophon 2.0
H8/3802, H8/38004, H8/38002S, H8/38104 Group

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